Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

Abstract: The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.

Abstract: In a memory module, encryption information is received from an external source and stored exclusively within a non-persistent storage element such that the encryption information is expunged from the memory module upon power loss. Write data is received and encrypted using the encryption information stored within the non-persistent storage element to produce encrypted data which is stored, in turn, within a nonvolatile storage of the memory module.

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

Abstract: The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.

Abstract: An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.

Abstract: The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.

Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller.

Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller.

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller.

Abstract: Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.

Abstract: Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.

Abstract: Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.

Abstract: Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.

Abstract: Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.

Abstract: Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.