Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.

Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction paths.

Abstract: Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

Abstract: A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate.

Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.