Patents by Inventor Badih El-Kareh
Badih El-Kareh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10229922Abstract: A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.Type: GrantFiled: May 12, 2016Date of Patent: March 12, 2019Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes
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Patent number: 9583195Abstract: Memory cells and methods for programming and erasing a memory cell by utilizing a buried select line are described. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.Type: GrantFiled: August 29, 2013Date of Patent: February 28, 2017Assignee: Micron Technology, Inc.Inventor: Badih El-Kareh
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Patent number: 9553177Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.Type: GrantFiled: June 18, 2015Date of Patent: January 24, 2017Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
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Publication number: 20160254270Abstract: A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.Type: ApplicationFiled: May 12, 2016Publication date: September 1, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Badih El-Kareh, Leonard Forbes
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Patent number: 9361981Abstract: Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type; biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; and injecting electrons into a charge-storage node of the selected memory cell from the second conductive region. The first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained.Type: GrantFiled: February 12, 2014Date of Patent: June 7, 2016Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes
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Publication number: 20150287815Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
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Patent number: 9076835Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.Type: GrantFiled: April 2, 2013Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
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Patent number: 9076662Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.Type: GrantFiled: August 6, 2013Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes
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Patent number: 8847359Abstract: High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.Type: GrantFiled: August 6, 2009Date of Patent: September 30, 2014Assignee: Texas Instruments IncorporatedInventors: Scott Gerard Balster, Hiroshi Yasuda, Philipp Steinmann, Badih El-Kareh
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Publication number: 20140169103Abstract: Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type; biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; and injecting electrons into a charge-storage node of the selected memory cell from the second conductive region. The first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained.Type: ApplicationFiled: February 12, 2014Publication date: June 19, 2014Applicant: Micron Technology, Inc.Inventors: Badih EL-KAREH, Leonard FORBES
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Patent number: 8654592Abstract: Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures.Type: GrantFiled: June 12, 2007Date of Patent: February 18, 2014Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes
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Publication number: 20140003158Abstract: Memory cells and methods for programming and erasing a memory cell by utilizing a buried select line are described. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: Micron Technology, Inc.Inventor: Badih El-Kareh
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Patent number: 8618633Abstract: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.Type: GrantFiled: January 24, 2012Date of Patent: December 31, 2013Assignee: Micron Technology, Inc.Inventor: Badih El-Kareh
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Publication number: 20130313618Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.Type: ApplicationFiled: August 6, 2013Publication date: November 28, 2013Applicant: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes
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Publication number: 20130234287Abstract: A high-precision capacitor includes a first degenerately doped polysilicon plate, a second degenerately doped polysilicon plate, and a dielectric material disposed between the first and the second degenerately doped polysilicon plates. The first degenerately doped polysilicon plate may be formed by performing POCL (phosphorus oxychloride) diffusion, and performing ion implantation through the POCL oxide to replenish the loss of dopants. The second degenerately doped polysilicon plate may be formed by performing POCL doping. The high-precision capacitor may exhibit a voltage coefficient of capacitance (VCC) comparable to a Metal-Insulator-Metal capacitor, however, with a dielectric of higher quality.Type: ApplicationFiled: May 3, 2012Publication date: September 12, 2013Applicant: Dongbu HiTek Co., Ltd.Inventors: Badih EL-KAREH, JONG HO LEE, DONGSEOK KIM, CHANG EUN LEE, Jung-Joo KIM
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Patent number: 8530952Abstract: Memory cells and methods for programming and erasing a memory cell by utilizing a buried select line are described. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.Type: GrantFiled: August 23, 2007Date of Patent: September 10, 2013Assignee: Micron Technology, Inc.Inventor: Badih El-Kareh
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Patent number: 8502280Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.Type: GrantFiled: April 13, 2011Date of Patent: August 6, 2013Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes
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Patent number: 8450179Abstract: A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.Type: GrantFiled: February 2, 2007Date of Patent: May 28, 2013Assignee: Texas Instruments Deutschland GmbHInventors: Badih El-Kareh, Hiroshi Yasuda, Scott Balster
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Patent number: 8415720Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.Type: GrantFiled: June 29, 2011Date of Patent: April 9, 2013Assignee: Dongbu HiTek Co., Ltd.Inventors: Badih El-Kareh, Kyu Ok Lee, Joo Hyung Kim, Jung Joo Kim
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Patent number: 8409959Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.Type: GrantFiled: March 13, 2007Date of Patent: April 2, 2013Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn