Patents by Inventor Badih El-Kareh

Badih El-Kareh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080308855
    Abstract: Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 18, 2008
    Inventors: Badih El-Kareh, Leonard Forbes
  • Publication number: 20080227262
    Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 18, 2008
    Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
  • Publication number: 20080048231
    Abstract: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.
    Type: Application
    Filed: August 28, 2006
    Publication date: February 28, 2008
    Inventor: Badih El-Kareh
  • Publication number: 20080042199
    Abstract: The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
    Type: Application
    Filed: August 15, 2006
    Publication date: February 21, 2008
    Inventors: Joe R. Trogolo, Hiroshi Yasuda, Badih El-Kareh, Philipp Steinmann
  • Publication number: 20080026515
    Abstract: An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Badih El-Kareh, Hiroshi Yasuda, Scott Gerard Balster, Philipp Steinmann, Joe R. Trogolo
  • Patent number: 7312119
    Abstract: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: December 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Scott Gerard Balster, Badih El-Kareh, Philipp Steinman, Christoph Dirnecker
  • Publication number: 20070207585
    Abstract: A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type and a BiCMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type A method for fabricating a BICMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type comprises the steps of depositing a dielectric layer (24) over a semiconductor layer (14), depositing a gate conductor layer (26) over the dielectric layer (24), defining base regions (28, 30) of the first and second bipolar devices; removing the gate conductor layer (26) and the dielectric layer (24) in the base regions (28, 30) of the first and second bipolar devices, depositing a base layer (32) on the gate conductor layer (26) and on the exposed semiconductor layer (14) in the base regions (28, 30) of the first and second bipolar devices depositing an insulating layer (36) over said base layer (32), forming a photoresist layer (38) an
    Type: Application
    Filed: February 2, 2007
    Publication date: September 6, 2007
    Applicant: TEXAS INSTRUMENTS INCOPRORATED
    Inventors: Badih El-Kareh, Hiroshi Yasuda, Scott Balster
  • Patent number: 7217322
    Abstract: A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: May 15, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Scott Balster, Alfred Haeusler, Angelo Pinto, Manfred Schiekofer, Philipp Steinmann, Badih El-Kareh
  • Publication number: 20070069269
    Abstract: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
    Type: Application
    Filed: October 13, 2006
    Publication date: March 29, 2007
    Inventors: Scott Balster, Badih El-Kareh, Philipp Steinmann, Christoph Dirnecker
  • Patent number: 7192838
    Abstract: Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: March 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Philipp Steinmann, Scott Balster, Badih El-Kareh, Thomas Scharnagl
  • Publication number: 20070057281
    Abstract: An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
    Type: Application
    Filed: September 7, 2006
    Publication date: March 15, 2007
    Inventors: Badih El-Kareh, Scott Balster, Hiroshi Yasuda, Manfred Schiekofer
  • Patent number: 7144789
    Abstract: In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: December 5, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Badih El-Kareh, Scott Balster, Philipp Steinmann, Thomas Scharnagl, Manfred Schiekofer, Carl Willis
  • Patent number: 7130182
    Abstract: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: October 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Scott Balster, Badih El-Kareh, Philipp Steinmann, Christoph Dirnecker
  • Patent number: 7118981
    Abstract: In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: October 10, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Alfred Haeusler, Philipp Steinmann, Scott Balster, Badih El-Kareh
  • Publication number: 20060073672
    Abstract: An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.
    Type: Application
    Filed: September 23, 2005
    Publication date: April 6, 2006
    Inventors: Philipp Steinmann, Scott Balster, Badih El-Kareh, Thomas Scharnagl, Michael Schmitt
  • Publication number: 20050118771
    Abstract: A method of producing a vertical bipolar PNP transistor is disclosed. The phosphorous profile in the base layer is controlled. Carbon that is incorporated in the base layer in the vicinity of the base-collector junction suppresses the diffusion of phosphorous deeper than implanted in a subsequent thermal step. PNP transistors with a narrow phosphorous-doped base can thus be manufactured with a cut-off frequency increased from 23 GHz to 30 GHz.
    Type: Application
    Filed: October 28, 2004
    Publication date: June 2, 2005
    Inventors: Hiroshi Yasuda, Badih El-Kareh, Scott Balster, Manfred Schiekofer
  • Publication number: 20050098093
    Abstract: A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.
    Type: Application
    Filed: September 2, 2004
    Publication date: May 12, 2005
    Inventors: Jeffrey Babcock, Scott Balster, Alfred Haeusler, Angelo Pinto, Manfred Schiekofer, Philipp Steinmann, Badih El-Kareh
  • Publication number: 20050054170
    Abstract: Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 10, 2005
    Inventors: Philipp Steinmann, Scott Balster, Badih El-Kareh, Thomas Scharnagl
  • Publication number: 20050014341
    Abstract: In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.
    Type: Application
    Filed: April 8, 2004
    Publication date: January 20, 2005
    Inventors: Badih El-Kareh, Scott Balster, Philipp Steinmann, Thomas Scharnagl, Manfred Schiekofer, Carl Willis
  • Publication number: 20050001236
    Abstract: In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.
    Type: Application
    Filed: April 15, 2004
    Publication date: January 6, 2005
    Inventors: Alfred Haeusler, Philipp Steinmann, Scott Balster, Badih El-Kareh