Patents by Inventor Baiju Patel

Baiju Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100299479
    Abstract: For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
    Type: Application
    Filed: September 17, 2009
    Publication date: November 25, 2010
    Inventors: Mark Buxton, Ernie Brickell, Quinn A. Jacobson, Hong Wang, Baiju Patel
  • Patent number: 7610448
    Abstract: For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: October 27, 2009
    Assignee: Intel Corporation
    Inventors: Mark Buxton, Ernie Brickell, Quinn A. Jacobson, Hong Wang, Baiju Patel
  • Publication number: 20080162816
    Abstract: For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Mark Buxton, Ernie Brickell, Quinn A. Jacobson, Hong Wang, Baiju Patel
  • Publication number: 20070157211
    Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 5, 2007
    Inventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James Held
  • Publication number: 20070150900
    Abstract: Data structure creation, organization and management techniques for data local to user-level threads are provided. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 28, 2007
    Inventors: Richard Hankins, Gautham Chinya, Hong Wang, David Poulsen, Shirish Aundhe, John Shen, Sanjiv Shah, Baiju Patel
  • Publication number: 20070079301
    Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju Patel, Jason Brandt, Anil Aggarwal, John Reid
  • Publication number: 20070074217
    Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine resides in user space and may be part of a runtime library. The library may also include monitoring logic that monitors execution of a shredded program and provides scheduling hints, based on shred dependence information, to the scheduler. In addition, the scheduler may further optimize shred scheduling by taking into account information about a system's configuration of thread execution hardware. Other embodiments are also described and claimed.
    Type: Application
    Filed: September 26, 2005
    Publication date: March 29, 2007
    Inventors: Ryan Rakvic, Richard Hankins, Hong Wang, Trung Diep, Xinmin Tain, Paul Petersen, Sanjiv Shah, John Shen, Gautham Chinya, Shivnandan Kaushik, Bryant Bigbee, Baiju Patel, Douglas Armstrong
  • Publication number: 20070006231
    Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Hong Wang, John Shen, Ed Grochowski, James Held, Bryant Bigbee, Shivnandan Kaushik, Gautham Chinya, Xiang Zou, Per Hammarlund, Xinmin Tian, Anil Aggarwal, Scott Rodgers, Prashant Sethi, Baiju Patel, Richard Hankins
  • Publication number: 20060282839
    Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
    Type: Application
    Filed: June 13, 2005
    Publication date: December 14, 2006
    Inventors: Richard Hankins, Gautham Chinya, Hong Wang, Shivnandan Kaushik, Bryant Bigbee, John Shen, Trung Diep, Xiang Zou, Baiju Patel, Paul Petersen, Sanjiv Shah, Ryan Rakvic, Prashant Sethi
  • Publication number: 20060271932
    Abstract: Operating system services are transparently triggered for thread execution resources (“sequencers”) that are sequestered from view of the operating system. A “surrogate” thread that is managed by, and visible to, the operating system is utilized to acquire OS services on behalf of a sequestered sequencer. Multi-shred contention for shred-specific resources may thus be alleviated. Other embodiments are also described and claimed.
    Type: Application
    Filed: May 13, 2005
    Publication date: November 30, 2006
    Inventors: Gautham Chinya, Hong Wang, Richard Hankins, Shivnandan Kaushik, Bryant Bigbee, John Shen, Prashant Sethi, Baiju Patel, John Reid
  • Publication number: 20060224858
    Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.
    Type: Application
    Filed: April 5, 2005
    Publication date: October 5, 2006
    Inventors: Hong Wang, Gautham Chinya, Richard Hankins, Shivnandan Kaushik, Bryant Bigbee, Per Hammarlund, Xiang Zou, Jason Brandt, Prashant Sethi, Douglas Carmean, Baiju Patel, John Shen, Scott Rodgers, Ryan Rakvic, John Reid, David Poulsen, Sanjiv Shah, James Held, James Abel
  • Publication number: 20060150183
    Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Gautham Chinya, Hong Wang, Xiang Zou, James Held, Prashant Sethi, Trung Diep, Anil Aggarwal, Baiju Patel, Shiv Kaushik, Bryant Bigbee, John Shen, Richard Hankins, John Reid
  • Publication number: 20060150184
    Abstract: Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Richard Hankins, Hong Wang, Gautham Chinya, Trung Diep, Shivnandan Kaushik, Bryant Bigbee, John Shen, Asit Mallick, Baiju Patel, James Held, Milind Girkar, Prashant Sethi, Xinmin Tian
  • Patent number: 6915431
    Abstract: A system and method of providing security mechanisms for securing traffic communicated from a server system to a client system independent of the state of the client system. The server system determines whether the client system has entered an operational state. When the client system is operational, key exchange processes are initiated between the two systems, the results of the key exchange processes being the parameters for use in securing traffic communication between the two systems. The results are stored in the client system. The results are inhibited from being updated in the client system until the server system is successful in completely executing another set of key exchange processes. The results are updated with the results obtained from successful execution of the other set of key exchange processes if the execution of the other set is successful. The traffic communication is thus secured based on whatever results are stored in the client system.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: July 5, 2005
    Assignee: Intel Corporation
    Inventors: Anil Vasudevan, Baiju Patel, Marc Jalfon