Patents by Inventor Baiju V. Patel

Baiju V. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110078389
    Abstract: A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventors: Baiju V. Patel, Rajeev Gopalakrishna, Andrew F. Glew, Robert J. Kushlis, Don Alan Van Dyke, Joseph Frank Cihula, Asit K. Mallick, James B. Crossland, Gilbert Neiger, Scott Dion Rodgers, Martin Guy Dixon, Mark Jay Charney, Jocob Gottlieb
  • Patent number: 7810083
    Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: October 5, 2010
    Assignee: Intel Corporation
    Inventors: Gautham N. Chinya, Hong Wang, Xiang Zou, James Paul Held, Prashant Sethi, Trung Diep, Anil Aggarwal, Baiju V. Patel, Shiv Kaushik, Bryant Bigbee, John Shen, Richard A. Hankins, John L. Reid
  • Patent number: 7743233
    Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: June 22, 2010
    Assignee: Intel Corporation
    Inventors: Hong Wang, Gautham N. Chinya, Richard A. Hankins, Shivnandan D. Kaushik, Bryant Bigbee, John Shen, Per Hammarlund, Xiang Zou, Jason W. Brandt, Prashant Sethi, Douglas M. Carmean, Baiju V. Patel, Scott Dion Rodgers, Ryan N. Rakvic, John L. Reid, David K. Poulsen, Sanjiv M. Shah, James Paul Held, James Charles Abel
  • Publication number: 20080148259
    Abstract: Methods, data structures, instructions, and techniques for structured exception handling for user-level threads in a multi-threading system are provided. Registered filter routines may be dispatched to a thread unit not managed by the operating system (OS). The dispatch may occur by allowing an OS-managed thread unit (proxy) to invoke the OS-provided structured exception handling service (including dispatcher) on behalf of the sequestered thread unit. Alternatively, an OS-managed thread unit may include dispatch code and may, without OS intervention, dispatch the filter routine to the sequestered thread unit. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, David K. Poulsen, Shirish Aundhe, Baiju V. Patel, Sanjiv M. Shah
  • Patent number: 7370348
    Abstract: A controller for controlling communications between a system and a transport medium includes a receiving circuit to receive data and associated security control information. A first cryptographic engine cryptographically processes the data received from the transport medium based on the security control information. The controller also includes a second cryptographic engine to process data generated in the system according to a security protocol before transmission to the transport medium.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: May 6, 2008
    Assignee: Intel Corporation
    Inventors: Baiju V. Patel, Uri Elzur
  • Patent number: 7363320
    Abstract: A method and system is provided for correlating data. A data tuple includes a unique record ID and a record. At least one data tuple is sent from a data supplier to a data user. An entity correlator receives at least one pair of the record ID and an identifying ID from a data supplier. The data user forwards a record ID list to the entity correlator. The record ID list includes at least one record ID. The entity correlator generates an entity list and sends it to the data user. The entity list correlates each entity in the entity list with the at least one record ID.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventor: Baiju V. Patel
  • Patent number: 7178034
    Abstract: A method and apparatus for strong authentication and proximity-based access retention is presented. In this regard, an authentication agent is introduced to securely communicate with a key device associated with a user to identify the user, retrieve credentials for the user, securely communicate a session key to the key device, and identify the user who is requesting access to target resource(s) based on the user's credentials while the user's key device is proximate to the target resource(s).
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Joseph F. Cihula, Baiju V. Patel
  • Publication number: 20040205080
    Abstract: A method and system is provided for correlating data. A data tuple includes a unique record ID and a record. At least one data tuple is sent from a data supplier to a data user. An entity correlator receives at least one pair of the record ID and an identifying ID from a data supplier. The data user forwards a record ID list to the entity correlator. The record ID list includes at least one record ID. The entity correlator generates an entity list and sends it to the data user. The entity list correlates each entity in the entity list with the at least one record ID.
    Type: Application
    Filed: May 4, 2004
    Publication date: October 14, 2004
    Applicant: Intel Corporation
    Inventor: Baiju V. Patel
  • Publication number: 20040128500
    Abstract: A method and apparatus for strong authentication and proximity-based access retention is presented. In this regard, an authentication agent is introduced to securely communicate with a key device associated with a user to identify the user, retrieve credentials for the user, securely communicate a session key to the key device, and identify the user who is requesting access to target resource(s) based on the user's credentials while the user's key device is proximate to the target resource(s).
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Joseph F. Cihula, Baiju V. Patel
  • Publication number: 20020004900
    Abstract: Secure anonymous communication between a first party and a second party is accomplished by establishing an identity of the first party with a third party, obtaining an anonymous certificate having a selected attribute by the first party from the third party, and presenting the anonymous certificate by the first party to the second party for verification to establish the anonymous communication.
    Type: Application
    Filed: September 4, 1998
    Publication date: January 10, 2002
    Inventor: BAIJU V. PATEL
  • Patent number: 6327660
    Abstract: Briefly, one embodiment of the present invention relates to a method comprising the act of providing a communication link between a first electronic system and a second electronic system. Prior to booting of an operating system of the first electronic system, the communication link is secured to protect the integrity of data transferred over the communication link.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: December 4, 2001
    Assignee: Intel Corporation
    Inventor: Baiju V. Patel
  • Patent number: 6317849
    Abstract: An apparatus within a device, such as an integrated circuit, for controlling available capabilities of the device. The apparatus includes an EEPROM storing a configuration control word having at least one bit, a configuration control mask having at least one bit, and logic to select a first operating mode of the device when the configuration control word does not match the configuration control mask and to select a second operating mode of the device when the configuration control word matches the configuration control mask. The first operating mode may indicate full capabilities of the device and the second operating mode may indicate a set of reduced capabilities of the device. Additional logic in the device implements a “write once” feature for irrevocably setting the configuration control word to match the configuration control mask, thereby permanently selecting the second operating mode (e.g., reduced capabilities).
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: November 13, 2001
    Assignee: Intel Corporation
    Inventor: Baiju V. Patel
  • Patent number: 5533020
    Abstract: A method and apparatus for scheduling the transmission of a number of data streams over a common communications link, where each of the data streams conforms to a corresponding set of flow control parameters. Each of the data streams to be transmitted on the communications link is stored in a corresponding queue. The status of each queue is maintained, and a target transmission time is calculated for each queue. Signals are then generated for each queue at a time at least after the target transmission time, and these signals are used to indicate to a corresponding queue that is can transmit a cell on the link. Upon reception of a corresponding signal, a queue then transmits at least one cell onto the communications link.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: July 2, 1996
    Assignee: International Business Machines Corporation
    Inventors: Jonathan W. Byrn, Gary S. Delp, Philip L. Leichty, Baiju V. Patel, Kevin G. Plotz, Frank A. Schaffa, Marc H. Willebeek-LeMair
  • Patent number: 5337311
    Abstract: In standard token-based LANs (e.g., FDDI, Token Ring) an equal share of the ring bandwidth is made available to each node. Certain nodes (e.g., bridges, routers, servers) require a larger representation (bandwidth) than other nodes. A surrogate (bridge/router) node is presented which achieves this in a standard compliant manner. The bridge/router may serve as a surrogate on each ring representing multiple stations from the other ring. The multiplicity of stations is adjusted either statically or dynamically to provide sufficient added bandwidth to the surrogate to reduce delay and packet loss characteristic of the conventional single station bridge or router. The increased bandwidth utilization and FDDI ring performance resulting from the implementation of this invention is transparent to the individual stations and the ring in a way that is advantageous to both single media and multimedia usages within defined network local and non-local areas.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: August 9, 1994
    Assignee: International Business Machines Corporation
    Inventors: Louis P. Herzberg, Baiju V. Patel, Antonio Ruiz, Frank A. Schaffa, Marc H. Willebeek-LeMair
  • Patent number: 5282199
    Abstract: A method and apparatus allow the interoperability of a token ring packet data network managed by the timed-token protocol (FDDI-I) and a TDM network (FDDI-II) with a given bandwidth allocation assigned to the packet data timed-token protocol. Only a single token is used, and the delay and loss of packets which cannot be transmitted on account of limited bandwidth is reduced. The flow of packets into the slots of the communications ring following the TDM protocol is controlled by varying the amount of time in which the token is held by the interface between the two communication rings. That is, the time in which the token is held by the interface is a function of the number TDM slots allocated to the transmission of packet data.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: January 25, 1994
    Assignee: International Business Machines Corporation
    Inventors: Louis P. Herzberg, Baiju V. Patel, Antonio Ruiz, Frank A. Schaffa, Marc H. Willebeek-LeMair