Abstract: Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

Abstract: Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.

Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Abstract: Data structure creation, organization and management techniques for data local to user-level threads are provided. In one embodiment, a method includes generating, for a user-level thread (“shred”) to run on a thread unit that is not managed by an operating system (“OS”), a storage area for local data and maintaining state in the storage area across a context switch from the thread unit that is not managed by the OS to a second thread unit that is managed by the OS. Other embodiments are also described and claimed.

Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

Abstract: A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.

Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Abstract: Methods, data structures, instructions, and techniques for structured exception handling for user-level threads in a multi-threading system are provided. Registered filter routines may be dispatched to a thread unit not managed by the operating system (OS). The dispatch may occur by allowing an OS-managed thread unit (proxy) to invoke the OS-provided structured exception handling service (including dispatcher) on behalf of the sequestered thread unit. Alternatively, an OS-managed thread unit may include dispatch code and may, without OS intervention, dispatch the filter routine to the sequestered thread unit. Other embodiments are also described and claimed.

Abstract: A controller for controlling communications between a system and a transport medium includes a receiving circuit to receive data and associated security control information. A first cryptographic engine cryptographically processes the data received from the transport medium based on the security control information. The controller also includes a second cryptographic engine to process data generated in the system according to a security protocol before transmission to the transport medium.

Abstract: A method and system is provided for correlating data. A data tuple includes a unique record ID and a record. At least one data tuple is sent from a data supplier to a data user. An entity correlator receives at least one pair of the record ID and an identifying ID from a data supplier. The data user forwards a record ID list to the entity correlator. The record ID list includes at least one record ID. The entity correlator generates an entity list and sends it to the data user. The entity list correlates each entity in the entity list with the at least one record ID.

Abstract: A method and apparatus for strong authentication and proximity-based access retention is presented. In this regard, an authentication agent is introduced to securely communicate with a key device associated with a user to identify the user, retrieve credentials for the user, securely communicate a session key to the key device, and identify the user who is requesting access to target resource(s) based on the user's credentials while the user's key device is proximate to the target resource(s).

Abstract: A method and system is provided for correlating data. A data tuple includes a unique record ID and a record. At least one data tuple is sent from a data supplier to a data user. An entity correlator receives at least one pair of the record ID and an identifying ID from a data supplier. The data user forwards a record ID list to the entity correlator. The record ID list includes at least one record ID. The entity correlator generates an entity list and sends it to the data user. The entity list correlates each entity in the entity list with the at least one record ID.

Abstract: A method and apparatus for strong authentication and proximity-based access retention is presented. In this regard, an authentication agent is introduced to securely communicate with a key device associated with a user to identify the user, retrieve credentials for the user, securely communicate a session key to the key device, and identify the user who is requesting access to target resource(s) based on the user's credentials while the user's key device is proximate to the target resource(s).

Abstract: Secure anonymous communication between a first party and a second party is accomplished by establishing an identity of the first party with a third party, obtaining an anonymous certificate having a selected attribute by the first party from the third party, and presenting the anonymous certificate by the first party to the second party for verification to establish the anonymous communication.

Abstract: Briefly, one embodiment of the present invention relates to a method comprising the act of providing a communication link between a first electronic system and a second electronic system. Prior to booting of an operating system of the first electronic system, the communication link is secured to protect the integrity of data transferred over the communication link.

Abstract: An apparatus within a device, such as an integrated circuit, for controlling available capabilities of the device. The apparatus includes an EEPROM storing a configuration control word having at least one bit, a configuration control mask having at least one bit, and logic to select a first operating mode of the device when the configuration control word does not match the configuration control mask and to select a second operating mode of the device when the configuration control word matches the configuration control mask. The first operating mode may indicate full capabilities of the device and the second operating mode may indicate a set of reduced capabilities of the device. Additional logic in the device implements a “write once” feature for irrevocably setting the configuration control word to match the configuration control mask, thereby permanently selecting the second operating mode (e.g., reduced capabilities).

Abstract: A method and apparatus for scheduling the transmission of a number of data streams over a common communications link, where each of the data streams conforms to a corresponding set of flow control parameters. Each of the data streams to be transmitted on the communications link is stored in a corresponding queue. The status of each queue is maintained, and a target transmission time is calculated for each queue. Signals are then generated for each queue at a time at least after the target transmission time, and these signals are used to indicate to a corresponding queue that is can transmit a cell on the link. Upon reception of a corresponding signal, a queue then transmits at least one cell onto the communications link.