Abstract: In an example, a semiconductor device includes an active trench region and an intersecting trench. The active region includes an active shield electrode and the intersecting trench includes an intersecting shield electrode. A coupling trench region connects the active trench region to the intersecting trench region. The coupling trench region includes a coupling shield electrode. The coupling shield electrode and the intersecting shield electrode are provided proximate to a termination mesa region. One or more of the coupling shield electrode or the intersecting shield electrode is thinner than the active shield electrode. The thinner shield electrode reduces depletion in the termination mesa region to improve, among other things, breakdown voltage performance.

Abstract: An accumulation MOSFET includes a plurality of device cells. Each device cell includes a mesa adjoining a vertical trench is disposed in a doped semiconductor substrate. The mesa has a top mesa portion disposed on a bottom mesa portion. The top mesa portion has a width that is narrower than a width of the bottom mesa portion. The vertical trench adjoining the mesa has a top trench portion and a bottom trench portion. The top trench portion has a width that is wider than a width of the bottom trench portion. A dielectric is disposed on a sidewall of the vertical trench. A gate electrode disposed in the top trench portion forms an accumulation channel region in the top mesa portion and a shield electrode disposed in the bottom trench portion forms a depletion drift region in the bottom mesa portion.

Abstract: A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.

Abstract: In one general aspect, an apparatus can include a substrate having a semiconductor region, and a trench defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode disposed in the trench and insulated from the sidewall of the trench by a shield dielectric, the shield dielectric having a low-k dielectric portion and a high-k dielectric portion. The apparatus can include a gate electrode disposed in the trench and at least partially surrounded by a gate dielectric, and an inter-electrode dielectric disposed between the shield electrode and the gate electrode.

Abstract: In a general aspect, a vertical transistor can include a semiconductor region of a first conductivity type, and a plurality of perpendicularly intersecting trenches having a shielded gate structure of the vertical transistor disposed therein. A mesa of the semiconductor region can be defined by the plurality of perpendicularly intersecting trenches. The mesa can include a proximal end portion having a first doping concentration of the first conductivity type, a distal end portion having the first doping concentration of the first conductivity type, and a central portion disposed between the proximal end portion and the distal end portion. The central portion can have a second doping concentration of the first conductivity type that is less than the first doping concentration.

Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

Abstract: A system for authenticating an individual's location activity includes a mobile communications device connected to a network and in electronic communication with at least one other computer. The mobile communications device is configured to authenticate the individual's presence at a location using biometric data entered by the individual. The mobile communications device has applications stored thereon to access location information for the mobile communications device using a GPS application stored on the mobile communications device and to access time information for the mobile communications device from a clock application stored on the mobile communications device. The mobile communications devices creates a digital signature that authenticates an individual's location activity by storing an encrypted digital certificate comprising a hash calculation using the biometric data, a validation key generated by authenticating the biometric data, the location information, and the time information.

Abstract: In some aspects, the techniques described herein relate to a circuit including: a metal-oxide semiconductor field-effect transistor (MOSFET) including a gate, a source, and a drain; and a snubber circuit coupled between the drain and the source, the snubber circuit including: a diode having a cathode and an anode, the cathode being coupled with the drain; a capacitor having a first terminal coupled with the anode, and a second terminal coupled with the source; and a resistor having a first terminal coupled with the anode and the first terminal of the capacitor, and a second terminal coupled with the source.

Abstract: A method includes defining a plurality of trenches of a first type that extend in a longitudinal direction in a semiconductor substrate, and defining a trench of a second type extending in a lateral direction and intersecting the plurality of trenches of the first type. The trench of the second type is in fluid communication with each of the intersected plurality of trenches of the first type. The method further includes disposing a shield poly layer in the plurality of trenches of the first type and the trench of the second type, disposing an inter-poly dielectric layer and a gate poly layer above the shield poly layer in the plurality of trenches of the first type and the trench of the second type, and forming an electrical contact to the shield poly layer through an opening in the inter-poly dielectric layer and the gate poly layer disposed in the trench of the second type.

Abstract: A device includes a mesa disposed between a pair of vertical trenches in a semiconductor substrate. A gate electrode is disposed in each of the pair of vertical trenches, and a shield electrode is disposed below each of the gate electrodes in the pair of vertical trenches. The device further includes a bridge connection trench traversing the mesa. The bridge connection trench is in fluid communication with each of the pair of vertical trenches. A bridge shield electrode is disposed in the bridge connection trench and is coupled to the shield electrode disposed below each of the gate electrodes in the pair of vertical trenches.

Abstract: A system for authenticating an individual's location activity includes a mobile communications device connected to a network and in electronic communication with at least one other computer. The mobile communications device is configured to authenticate the individual's presence at a location using biometric data entered by the individual. The mobile communications device has applications stored thereon to access location information for the mobile communications device using a GPS application stored on the mobile communications device and to access time information for the mobile communications device from a clock application stored on the mobile communications device. The mobile communications devices creates a digital signature that authenticates an individual's location activity by storing an encrypted digital certificate comprising a hash calculation using the biometric data, a validation key generated by authenticating the biometric data, the location information, and the time information.

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

Abstract: Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section including a first thickness, and a second gate insulator section including a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.

Abstract: Systems and methods for expert-assisted classification are described herein. An example method for evaluating an expert-assisted classifier can include providing a cascade classifier including a plurality of classifier stages; and providing a simulated expert stage between at least two of the classifier stages. The simulated expert stage can be configured to validate or contradict an output of one of the at least two classifier stages. The method can also include classifying each of a plurality of records into one of a plurality of categories using the cascade classifier combined with the simulated expert stage; and determining whether the simulated expert stage improves performance of the cascade classifier.

Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.

Abstract: A cloud security system and method designed to protect users' data in case of accidental leaks in a cloud computing environment. Secured hashing of the names of folders stored on the cloud data storage are generated and persisted using multiple iterations of cryptographic hash functions along with a concatenated random number for each of the folder names, thereby providing protection against vulnerability of the folder names. The proposed system is a dual-layer framework consisting of a control layer and a data layer. The control layer is responsible for cryptographic hashing and persistence of the folder name, hashed name, salt, and iterations in a database. The control layer communicates with the data layer and provides the hashed folder names to persist the user data cloud storage.

Abstract: An electronic device can include an enhancement-mode high electron mobility transistor (HEMT) that includes a source electrode; a drain electrode; and a gate. In an embodiment, the gate can correspond to spaced-apart gate electrodes and a space disposed between the spaced-apart gate electrodes, wherein the first space has a width configured such that, a continuous depletion region forms across all of the width of the first space. In another embodiment, the gate can be a gate electrode having a nonuniform thickness along a line in a gate width direction. In another aspect, a method of using the electronic device can include, during a transient period when the HEMT is in an off-state, flowing current from the drain electrode to the source electrode when Vds>?Vth+Vgs.

Abstract: A system for authenticating an individual's location activity includes a mobile communications device connected to a network and in electronic communication with at least one other computer. The mobile communications device is configured to authenticate the individual's presence at a location using biometric data entered by the individual. The mobile communications device has applications stored thereon to access location information for the mobile communications device using a GPS application stored on the mobile communications device and to access time information for the mobile communications device from a clock application stored on the mobile communications device. The mobile communications devices creates a digital signature that authenticates an individual's location activity by storing an encrypted digital certificate comprising a hash calculation using the biometric data, a validation key generated by authenticating the biometric data, the location information, and the time information.