Patents by Inventor Balaji Padmanabhan

Balaji Padmanabhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220407411
    Abstract: In some aspects, the techniques described herein relate to a circuit including: a metal-oxide semiconductor field-effect transistor (MOSFET) including a gate, a source, and a drain; and a snubber circuit coupled between the drain and the source, the snubber circuit including: a diode having a cathode and an anode, the cathode being coupled with the drain; a capacitor having a first terminal coupled with the anode, and a second terminal coupled with the source; and a resistor having a first terminal coupled with the anode and the first terminal of the capacitor, and a second terminal coupled with the source.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 22, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Dean E. PROBST, Joseph Andrew YEDINAK, Balaji PADMANABHAN, Peter A. BURKE, Jeffery A. NEULS, Ashok CHALLA
  • Publication number: 20220310813
    Abstract: A device includes a mesa disposed between a pair of vertical trenches in a semiconductor substrate. A gate electrode is disposed in each of the pair of vertical trenches, and a shield electrode is disposed below each of the gate electrodes in the pair of vertical trenches. The device further includes a bridge connection trench traversing the mesa. The bridge connection trench is in fluid communication with each of the pair of vertical trenches. A bridge shield electrode is disposed in the bridge connection trench and is coupled to the shield electrode disposed below each of the gate electrodes in the pair of vertical trenches.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 29, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zia HOSSAIN, Balaji PADMANABHAN, Sauvik CHOWDHURY
  • Publication number: 20220310802
    Abstract: A method includes defining a plurality of trenches of a first type that extend in a longitudinal direction in a semiconductor substrate, and defining a trench of a second type extending in a lateral direction and intersecting the plurality of trenches of the first type. The trench of the second type is in fluid communication with each of the intersected plurality of trenches of the first type. The method further includes disposing a shield poly layer in the plurality of trenches of the first type and the trench of the second type, disposing an inter-poly dielectric layer and a gate poly layer above the shield poly layer in the plurality of trenches of the first type and the trench of the second type, and forming an electrical contact to the shield poly layer through an opening in the inter-poly dielectric layer and the gate poly layer disposed in the trench of the second type.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 29, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Prasad VENKATRAMAN, Peter BURKE, Gary Horst LOECHELT, Balaji PADMANABHAN, Emily M. LINEHAN
  • Patent number: 11451538
    Abstract: A system for authenticating an individual's location activity includes a mobile communications device connected to a network and in electronic communication with at least one other computer. The mobile communications device is configured to authenticate the individual's presence at a location using biometric data entered by the individual. The mobile communications device has applications stored thereon to access location information for the mobile communications device using a GPS application stored on the mobile communications device and to access time information for the mobile communications device from a clock application stored on the mobile communications device. The mobile communications devices creates a digital signature that authenticates an individual's location activity by storing an encrypted digital certificate comprising a hash calculation using the biometric data, a validation key generated by authenticating the biometric data, the location information, and the time information.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 20, 2022
    Assignee: University of South Florida
    Inventors: Sriram Chellappan, Balaji Padmanabhan, Tanvir Hossain Bhuiyan, Arup Kanti Dey, Shaminur Rahman
  • Patent number: 11411077
    Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 9, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
  • Publication number: 20220077282
    Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 10, 2022
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
  • Publication number: 20220077290
    Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 10, 2022
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
  • Patent number: 11257916
    Abstract: Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section including a first thickness, and a second gate insulator section including a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Donald Zaremba, Gordon M. Grivna, Alexander Young
  • Patent number: 11138473
    Abstract: Systems and methods for expert-assisted classification are described herein. An example method for evaluating an expert-assisted classifier can include providing a cascade classifier including a plurality of classifier stages; and providing a simulated expert stage between at least two of the classifier stages. The simulated expert stage can be configured to validate or contradict an output of one of the at least two classifier stages. The method can also include classifying each of a plurality of records into one of a plurality of categories using the cascade classifier combined with the simulated expert stage; and determining whether the simulated expert stage improves performance of the cascade classifier.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 5, 2021
    Assignee: University of South Florida
    Inventors: Balaji Padmanabhan, Utkarsh Shrivastava, Vivek Kumar Singh
  • Patent number: 11127731
    Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: September 21, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Kirk K. Huang, Prasad Venkatraman, Emily M. Linehan, Zia Hossain
  • Patent number: 11055427
    Abstract: A cloud security system and method designed to protect users' data in case of accidental leaks in a cloud computing environment. Secured hashing of the names of folders stored on the cloud data storage are generated and persisted using multiple iterations of cryptographic hash functions along with a concatenated random number for each of the folder names, thereby providing protection against vulnerability of the folder names. The proposed system is a dual-layer framework consisting of a control layer and a data layer. The control layer is responsible for cryptographic hashing and persistence of the folder name, hashed name, salt, and iterations in a database. The control layer communicates with the data layer and provides the hashed folder names to persist the user data cloud storage.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: July 6, 2021
    Assignee: University of South Florida
    Inventors: Vivek Kumar Singh, Kaushik Dutta, Balaji Padmanabhan, Shalini Sasidharan
  • Patent number: 10811514
    Abstract: An electronic device can include an enhancement-mode high electron mobility transistor (HEMT) that includes a source electrode; a drain electrode; and a gate. In an embodiment, the gate can correspond to spaced-apart gate electrodes and a space disposed between the spaced-apart gate electrodes, wherein the first space has a width configured such that, a continuous depletion region forms across all of the width of the first space. In another embodiment, the gate can be a gate electrode having a nonuniform thickness along a line in a gate width direction. In another aspect, a method of using the electronic device can include, during a transient period when the HEMT is in an off-state, flowing current from the drain electrode to the source electrode when Vds>?Vth+Vgs.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 20, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, Balaji Padmanabhan
  • Publication number: 20200322331
    Abstract: A system for authenticating an individual's location activity includes a mobile communications device connected to a network and in electronic communication with at least one other computer. The mobile communications device is configured to authenticate the individual's presence at a location using biometric data entered by the individual. The mobile communications device has applications stored thereon to access location information for the mobile communications device using a GPS application stored on the mobile communications device and to access time information for the mobile communications device from a clock application stored on the mobile communications device. The mobile communications devices creates a digital signature that authenticates an individual's location activity by storing an encrypted digital certificate comprising a hash calculation using the biometric data, a validation key generated by authenticating the biometric data, the location information, and the time information.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 8, 2020
    Inventors: Sriram Chellappan, Balaji Padmanabhan, Tanvir Hossain Bhuiyan, Arup Kanti Dey, Shaminur Rahman
  • Publication number: 20200295149
    Abstract: Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section comprising a first thickness, and a second gate insulator section comprising a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.
    Type: Application
    Filed: June 24, 2019
    Publication date: September 17, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji PADMANABHAN, Prasad VENKATRAMAN, Zia HOSSAIN, Donald ZAREMBA, Gordon M. GRIVNA, Alexander YOUNG
  • Patent number: 10770381
    Abstract: In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: September 8, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Ali Salih, Prasad Venkatraman
  • Publication number: 20200243503
    Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Balaji Padmanabhan, Kirk K. Huang, Prasad Venkatraman, Emily M. Linehan, Zia Hossain
  • Patent number: 10707203
    Abstract: A method for forming a cascode rectifier structure includes providing a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are provided adjacent a major surface of the heterostructure and a control electrode is provided between the first and second current carrying electrode. A rectifier device is provided integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is provided further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is provided as a two terminal device.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Chun-Li Liu, Woochul Jeon, Jason McDonald
  • Patent number: 10658351
    Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: May 19, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Kirk K. Huang, Prasad Venkatraman, Emily M. Linehan, Zia Hossain
  • Patent number: 10593666
    Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 17, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Chun-Li Liu, Jason McDonald, Ali Salih, Alexander Young
  • Publication number: 20190305123
    Abstract: An electronic device can include an enhancement-mode high electron mobility transistor (HEMT) that includes a source electrode; a drain electrode; and a gate. In an embodiment, the gate can correspond to spaced-apart gate electrodes and a space disposed between the spaced-apart gate electrodes, wherein the first space has a width configured such that, a continuous depletion region forms across all of the width of the first space. In another embodiment, the gate can be a gate electrode having a nonuniform thickness along a line in a gate width direction. In another aspect, a method of using the electronic device can include, during a transient period when the HEMT is in an off-state, flowing current from the drain electrode to the source electrode when Vds>?Vth+Vgs.
    Type: Application
    Filed: February 27, 2019
    Publication date: October 3, 2019
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Woochul Jeon, Balaji Padmanabhan