Patents by Inventor Balaji Srinivasan

Balaji Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12062410
    Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Ashraf B. Islam, Jaydip Bharatkumar Patel, Yasir Mohsin Husain, Balaji Srinivasan, Nicolas L. Irizarry
  • Patent number: 12063160
    Abstract: A method for automatically connecting a computing device to one of a first virtual private network (VPN) and a second VPN over a network includes receiving, by the computing device from a server system over the network, availability indicia. The method also includes obtaining, by the computing device, a priority status indicating one of a high priority and a low priority. The method further includes determining, by the computing device, a connection VPN selected from the group consisting of the first VPN and the second VPN, the determination based on at least one of the availability indicia and the priority status of the computing device. The method includes establishing, by the computing device over the network, a connection to the connection VPN. The first VPN is prioritized over the second VPN.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: August 13, 2024
    Assignee: FMR LLC
    Inventors: Palavalli Govindaraju Raghunandan, Syed Muzamil, Hari Balaji Srinivasan
  • Patent number: 11935077
    Abstract: A system and method for real-time operational predictive scoring of components and services of an information technology system (ITS) for forecasting and assessing performance of the components of the ITS are provided. A data pipeline is configured to collect and store, in real-time, multiple time series signals corresponding to health, performance, and functionality of each of the components of the ITS. An operational predictive score (OPS) engine of a scoring module calculates an OPS for each of the time series signals. An OPS roll-up module of the scoring module calculates an OPS for each of the components and services in the ITS by aggregating the OPS for the individual time series signals. An alerting engine to notify operational issues and provide root cause analysis using OPS score decomposition. A visualization layer for OPS based analytics.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: March 19, 2024
    Assignee: VUNET SYSTEMS PRIVATE LIMITED
    Inventors: Jithesh Kaveetil, Ashwin Kumar Ramachandran, Balaji Srinivasan, Ganapathy Krishnamurthi
  • Patent number: 11900998
    Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Balaji Srinivasan, Sandeep Kumar Guliani, Mase J. Taub, Derchang Kau, Ashir G. Shah
  • Patent number: 11605429
    Abstract: Present disclosure relates to a method and a system for searching through a Ternary Content Addressable Memory (TCAM). The system comprises a Digital Light Processing System (DLP) receiving an input query. The DLP comprises a 2-Dimensional array of digital micro mirrors configured for reflecting light from one or more input sources in the TCAM to a predefined position. The system further comprises a detection screen having a detection area. The detection area is configured for generating an image of a resultant pixel according to the reflection of the light, wherein the resultant pixel corresponds to a search result for an input query.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 14, 2023
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY MADRAS (IIT MADRAS)
    Inventors: Ganesh Chennimalai Sankaran, Krishnamoorthy Sivalingam, Balaji Srinivasan
  • Patent number: 11460638
    Abstract: A fused fibre coupler comprising: a single mode fibre, SMF, and an orbital angular momentum fibre, OAMF, the fibres having a coupling portion in which the fibres are longitudinally aligned side by side and fused at least over a coupling length in which the SMF and OAMF are tapered such that the diameter of the SMF and the diameter of the OAMF give the fibres matching effective refractive indices for a single mode of the SMF and an orbital angular momentum, OAM, mode of the OAMF for a coupled wavelength of light.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: October 4, 2022
    Assignees: UNIVERSITY OF SOUTHAMPTON, INDIAN INSTITUTE OF TECHNOLOGY MADRAS
    Inventors: Shankar Pidishety, Balaji Srinivasan, Gilberto Brambilla
  • Publication number: 20220254443
    Abstract: The invention provides methods, apparatuses, and compositions for high-throughput amplification sequencing of specific target sequences in one or more samples. In some aspects, barcode-tagged polynucleotides are sequenced simultaneously and sample sources are identified on the basis of barcode sequences. In some aspects, sequencing data are used to determine one or more genotypes at one or more loci comprising a causal genetic variant. In some aspects, systems and methods of detecting genetic variation are provided.
    Type: Application
    Filed: January 24, 2022
    Publication date: August 11, 2022
    Applicant: MYRIAD WOMEN'S HEALTH, INC.
    Inventors: Hunter Richards, Eric Evans, Balaji Srinivasan, Subramaniam Srinivasan, Abhik Shah, A. Scott Patterson, Clement Chu
  • Publication number: 20220180905
    Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Ashraf B. Islam, Jaydip Bharatkumar Patel, Yasir Mohsin Husain, Balaji Srinivasan, Nicolas L. Irizarry
  • Patent number: 11342957
    Abstract: A switching system comprises a three-way radio switch for an onboard radio system. The radio switch includes a manual standby frequency switch that receives and displays a standby frequency input by a user; an automated standby frequency switch that receives and displays a standby frequency automatically input by the system; and an active frequency switch that shows a currently selected frequency. The active frequency switch receives and displays the frequency from the manual standby frequency switch, or receives and displays the frequency from the automated standby frequency switch. A processor is operative to monitor frequencies of the radio system in real-time; compare the frequencies of the radio system with frequencies from a database containing regional radio frequencies; trigger an alert when the frequencies of the radio system do not match the frequencies from the database; and send an updated standby radio frequency to the automated standby frequency switch.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 24, 2022
    Assignee: Honeywell International Inc.
    Inventors: Katarina Alexis Morowsky, Aaron J Gannon, Ivan Sandy Wyatt, Avery Burns, Balaji Srinivasan
  • Patent number: 11327066
    Abstract: A contaminant measurement system is provided. The system is operable to detect and measure a concentration level of a preselected contaminant, e.g., lead, in water disposed within a chamber of the system. The system includes a detection agent that is operable to interact with the preselected contaminant in the water. The detection agent can be a plurality of polymeric beads or a membrane, for example. The system has a sensing circuit that includes a pair of electrodes spaced from one another and both at least partially disposed in the water. A controller is communicatively coupled with the sensing circuit and is configured to receive one or more electric signals from the sensing circuit. The controller determines a parameter indicative of the concentration level of the preselected contaminant based on the one or more electrical signals. The controller then determines and outputs the concentration level of the preselected contaminant.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 10, 2022
    Assignee: Haier US Appliance Solutions, Inc.
    Inventors: Somak Chatterjee, Sharath Chandra Prasad, Allamneni Naga Tejaswini, Balaji Srinivasan, Moinuddin Mohd Bilal, Gregory Sergeevich Chernov, Andrew Reinhard Krause
  • Publication number: 20220133753
    Abstract: Methods and pharmaceutical compositions for use in treating diseases associated with insufficient activity of the pantothenate kinase enzyme (e.g., CASTOR diseases) are disclosed. The methods and compositions involve an effective amount of an active derivative of 4?-phosphopantetheine.
    Type: Application
    Filed: June 7, 2021
    Publication date: May 5, 2022
    Inventors: Gregor KOSEC, Ajda Podgorsek BERKE, Hrvoje PETKOVIC, Oda Cornelia Maria SIBON, Balaji SRINIVASAN, Susan J. HAYFLICK
  • Publication number: 20220108335
    Abstract: A system and method for real-time operational predictive scoring of components and services of an information technology system (ITS) for forecasting and assessing performance of the components of the ITS are provided. A data pipeline is configured to collect and store, in real-time, multiple time series signals corresponding to health, performance, and functionality of each of the components of the ITS. An operational predictive score (OPS) engine of a scoring module calculates an OPS for each of the time series signals. An OPS roll-up module of the scoring module calculates an OPS for each of the components and services in the ITS by aggregating the OPS for the individual time series signals. An alerting engine to notify operational issues and provide root cause analysis using OPS score decomposition. A visualization layer for OPS based analytics.
    Type: Application
    Filed: October 29, 2020
    Publication date: April 7, 2022
    Inventors: Jithesh Kaveetil, Ashwin Kumar Ramachandran, Balaji Srinivasan, Ganapathy Krishnamurthi
  • Publication number: 20220084589
    Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 17, 2022
    Applicant: Intel Corporation
    Inventors: Balaji Srinivasan, Sandeep Kumar Guliani, Mase J. Taub, DerChang Kau, Ashir G. Shah
  • Patent number: 11276465
    Abstract: A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Balaji Srinivasan, Mase J. Taub, DerChang Kau
  • Publication number: 20220059166
    Abstract: A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Inventors: Balaji Srinivasan, Mase J. Taub, DerChang Kau
  • Publication number: 20210327507
    Abstract: Present disclosure relates to a method and a system for searching through a Ternary Content Addressable Memory (TCAM). The system comprises a Digital Light Processing System (DLP) receiving an input query. The DLP comprises a 2-Dimensional array of digital micro mirrors configured for reflecting light from one or more input sources in the TCAM to a predefined position. The system further comprises a detection screen having a detection area. The detection area is configured for generating an image of a resultant pixel according to the reflection of the light, wherein the resultant pixel corresponds to a search result for an input query.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 21, 2021
    Inventors: Ganesh Sankaran, Krishnamoorthy Sivalingam, Balaji Srinivasan
  • Patent number: 11110419
    Abstract: A system and method are directed toward the synthesis of polymeric capsules using a phase inversion process by extrusion of polymeric droplets through a syringe-needle assembly or an iris-shutter mechanism. The polymeric solution may be prepared by dissolving PAN (polyacrylonitrile) polymer in DMF (Dimethyl Formamide) solvent at high temperature through continuous stirring. Following preparation of the capsules, further treatment was initiated using triethylamine in gelation bath to make the final product an efficient removal agent of water hardness.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 7, 2021
    Assignee: Haier US Appliance Solutions, Inc.
    Inventors: Somak Chatterjee, Sharath Chandra Prasad, Srinivas Pasham, Balaji Srinivasan, Gaurav Kumar Verma, Andrew Reinhard Krause, Gregory Sergeevich Chernov
  • Patent number: D954940
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: June 14, 2022
    Assignee: Cilag GmbH International
    Inventors: Sajayesh Vijayachandran, Arunachalam Muthuchidambaram, Arunkumar Radhakrishnan, Rushikesh Shrikant Suryawanshi, Balaji Srinivasan, Karthik Jayaraj, Haribaskaran Nagarathinam, Giri Prasanna Kumar Mathivanan, Gregory G. Scott
  • Patent number: D958360
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: July 19, 2022
    Assignee: Cilag GmbH International
    Inventors: Sajayesh Vijayachandran, Arunachalam Muthuchidambaram, Arunkumar Radhakrishnan, Rushikesh Shrikant Suryawanshi, Balaji Srinivasan, Karthik Jayaraj, Haribaskaran Nagarathinam, Giri Prasanna Kumar Mathivanan, Gregory G. Scott
  • Patent number: D963165
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: September 6, 2022
    Assignee: Cilag Gmbh International
    Inventors: Sajayesh Vijayachandran, Arunachalam Muthuchidambaram, Arunkumar Radhakrishnan, Rushikesh Shrikant Suryawanshi, Balaji Srinivasan, Karthik Jayaraj, Haribaskaran Nagarathinam, Giri Prasanna Kumar Mathivanan, Gregory G. Scott