Patents by Inventor Balaji Srinivasan

Balaji Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7310664
    Abstract: A network switch having a unified, adaptive management paradigm for wireless network devices is disclosed. The switch includes configurable ports for connecting devices. A software application running on the switch allows a network administrator to selectively configure each port to support either a wired device or wireless device. Configuration information and software images that are needed for operation of the wireless device are associated with the port. When a wireless device is first plugged into the switch port, it downloads its configuration directly from the switch port. By storing the configuration information and images at the switch and automatically downloading them to the wireless devices, the task of configuring the devices is greatly simplified for the network administrator. This is particularly advantageous in heterogeneous network environments that support both wired and wireless devices, and where wireless device are readily moved to different ports.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: December 18, 2007
    Assignee: Extreme Networks
    Inventors: Shehzad T. Merchant, Manish M. Rathi, Victor C. Lin, Vipin K. Jain, Jia-Ru Li, Amit K. Maitra, Matthew R. Peters, Derek H. Pitcher, Balaji Srinivasan
  • Patent number: 7304889
    Abstract: A serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: December 4, 2007
    Assignee: Intel Corporation
    Inventors: Matthew Goldman, Balaji Srinivasan, Hernan Castro
  • Publication number: 20070260540
    Abstract: A method and apparatus for providing a competitive bid from a provider comprising receiving billing data from a user, the billing data including provider information, location, and total bill amount. The method further comprising calculating a complex usage pattern based on the billing data and statistical data for the location. The method additionally comprising calculating a competitive bid for the user, based on the complex usage pattern and a pricing structure of the provider.
    Type: Application
    Filed: June 24, 2002
    Publication date: November 8, 2007
    Inventors: Victor Chau, Doug Hoople, Timothy Leung, Kirsty Nuttall, Muralidhar Ravuri, Joshua Roper, Peter Sovocool, Balaji Srinivasan, Colette Yee
  • Publication number: 20070214020
    Abstract: An insurance product class is defined which includes multiple data elements that are common to various insurance product types. Further, several classes derived from the insurance product class are defined, with each derived class extending the common data elements to include data elements that are specific to a certain insurance product type.
    Type: Application
    Filed: March 18, 2003
    Publication date: September 13, 2007
    Inventors: Balaji Srinivasan, Shan Wei, Ashfaq Jeelani, Lin Lee, Caroline Muralitharan
  • Publication number: 20070111871
    Abstract: An industrial roll includes: a substantially cylindrical metallic core; a rubber base layer that is adhered to and circumferentially overlies the core; a rubber top stock layer that circumferentially overlies the base layer; and a polyurethane coating that circumferentially overlies the top stock layer. In this configuration, the roll can provide improved abrasion-resistance, sheet release properties, and/or toughness compared to a roll with a rubber cover, but may provide these properties in a cover that is softer than a typical polyurethane cover.
    Type: Application
    Filed: November 8, 2005
    Publication date: May 17, 2007
    Inventors: William Butterfield, Dilip De, Balaji Srinivasan, Gary Kilbourne
  • Publication number: 20060274774
    Abstract: Methods, systems, and computer program products for dynamic network access device port and user device configuration are disclosed. According to one method, when a user device is connected to a port of a network access device, the type of user device is determined. The type of user device is used to locate a corresponding port configuration policy. The port to which the device is connected is dynamically configured based on the port configuration policy.
    Type: Application
    Filed: June 7, 2005
    Publication date: December 7, 2006
    Inventors: Balaji Srinivasan, Desikan Saravanan, Nick Suizo, Rajasekaran Nagarajan, Jeffrey Ronne, Abhay Gidwani, Wolfgang Lochner
  • Publication number: 20060262620
    Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
    Type: Application
    Filed: July 26, 2006
    Publication date: November 23, 2006
    Inventors: Matthew Goldman, Balaji Srinivasan, Hernan Castro
  • Patent number: 7116597
    Abstract: The various embodiments of the present invention provide high precision reference devices, methods, and systems. A high precision reference device may include a plurality of reference cells to receive bias voltages and to provide a cell reference, and an averaging stage coupled to the reference cells to generate an average reference that is the average of the cell references. Other devices, methods, and systems are also claimed and described.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: October 3, 2006
    Assignee: Intel Corporation
    Inventors: Matthew Goldman, Balaji Srinivasan, Kerry D. Tedrow, Paul D. Ruby
  • Patent number: 7106626
    Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventors: Matthew Goldman, Balaji Srinivasan, Hernan Castro
  • Publication number: 20050265098
    Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
    Type: Application
    Filed: August 3, 2005
    Publication date: December 1, 2005
    Inventors: Matthew Goldman, Balaji Srinivasan, Hernan Castro
  • Publication number: 20050261115
    Abstract: An industrial roll includes: a substantially cylindrical core having an outer surface; a polymeric cover circumferentially overlying the core outer surface, the cover including a base layer circumferentially overlying the core and a topstock layer overlying the base layer; and a sensing system. The sensing system includes: a plurality of piezoelectric sensors embedded in the cover base layer, the sensors configured to sense pressure experienced by the roll and provide signals related to the pressure; and a processor operatively associated with the sensors that processes signals provided by the sensors.
    Type: Application
    Filed: May 4, 2005
    Publication date: November 24, 2005
    Applicant: Myers Bigel Sibley & Sajovec, P.A.
    Inventors: Robert Moore, Eric Gustafson, Balaji Srinivasan
  • Publication number: 20050207418
    Abstract: A communication method is based on a communications standard such as, for example, asynchronous transfer mode (ATM), that defines a cell format 110 with a standard header 5 of a standard length M (for ATM, five octets). The method involves forming an abbreviated header 2 of length m<M, and sending a cell 100 including the abbreviated header 2 over a communications medium. In one example, the length of the abbreviated header 2 is two octets, which is substantially less than the five-octet length of a conventional ATM header 5, thus substantially reducing the proportion of cell overhead and increasing communications throughput capability.
    Type: Application
    Filed: March 16, 2004
    Publication date: September 22, 2005
    Inventors: Zhicheng Tang, Balaji Srinivasan
  • Patent number: 6831862
    Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: December 14, 2004
    Assignee: Intel Corporation
    Inventors: Kerry D. Tedrow, Balaji Srinivasan, Owen W. Jungroth
  • Patent number: 6717856
    Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a first drain bias network having an input suitable to couple to a FLASH cell. The apparatus also includes a second drain bias network having an input suitable to couple to a FLASH cell. The apparatus further includes an equalization circuit having a first node coupled to the input of the first drain bias network and having a second node coupled to the input of the second drain bias network and having a control signal to control operation of the equalization circuit.
    Type: Grant
    Filed: June 30, 2001
    Date of Patent: April 6, 2004
    Assignee: Intel Corporation
    Inventors: Balaji Srinivasan, Sandeep Guliani
  • Publication number: 20030214867
    Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Matthew Goldman, Balaji Srinivasan, Hernan Castro
  • Patent number: 6570789
    Abstract: An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: May 27, 2003
    Assignee: Intel Corporation
    Inventors: Ritesh Trivedi, Robert Baltar, Mark Bauer, Sandeep Guliani, Balaji Srinivasan
  • Publication number: 20030090949
    Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.
    Type: Application
    Filed: December 26, 2002
    Publication date: May 15, 2003
    Inventors: Kerry D. Tedrow, Balaji Srinivasan, Owen W. Jungroth
  • Patent number: 6542664
    Abstract: An improved highly doped waveguide is provided which comprises a waveguide employing an Er dopant and Pr sensitizer ions. The present invention also provides a method of efficient coupling from an optical source into a waveguide using a rotated optical element.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: April 1, 2003
    Assignee: Science & Technology Corporation &commat; UNM
    Inventors: Balaji Srinivasan, Ravinder K. Jain, Jason David Tafoya
  • Patent number: 6534248
    Abstract: The present invention relates generally to electro-optically active waveguide segments, and more particularly to the use of a selective voltage input to control the phase, frequency and/or amplitude of a propagating wave in the waveguide. Particular device structures and methods of manufacturing are described herein.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: March 18, 2003
    Assignee: Science and Technology Corporation &commat; UNM
    Inventors: Ravinder Jain, Balaji Srinivasan
  • Patent number: 6535423
    Abstract: An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: March 18, 2003
    Assignee: Intel Corporation
    Inventors: Ritesh Trivedi, Robert Baltar, Mark Bauer, Sandeep Guliani, Balaji Srinivasan