Patents by Inventor Balamurugan Balasubramanian
Balamurugan Balasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210342217Abstract: A method for diagnosing and repairing a first computing device that is not able to be booted due to a malfunction of the first computing device is provided. The method comprises providing a boot tool stored on a removable computer readable storage medium; allowing the first computing device to be booted using the boot tool; providing for communication between the first computing device and a remote help desk computing device over a network; remotely identifying the malfunction of the first computing device; and pushing at least one repair data file from the remote help desk computing device to the first computing device or downloading the at least one repair data file from the Internet using the first computing device, wherein the at least one repair data file is configured for repairing the first computing device so that the first computing device is bootable without use of the boot tool.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Applicant: Sutherland Global Services, Inc.Inventors: Balamurugan Balasubramanian, Naveen Kumaresan, Sanooj P S, Venkatesh Madhavan
-
Patent number: 11132250Abstract: A method for diagnosing and repairing a first computing device that is not able to be booted due to a malfunction of the first computing device is provided. The method comprises providing a boot tool stored on a removable computer readable storage medium; allowing the first computing device to be booted using the boot tool; providing for communication between the first computing device and a remote help desk computing device over a network; remotely identifying the malfunction of the first computing device; and pushing at least one repair data file from the remote help desk computing device to the first computing device or downloading the at least one repair data file from the Internet using the first computing device, wherein the at least one repair data file is configured for repairing the first computing device so that the first computing device is bootable without use of the boot tool.Type: GrantFiled: October 18, 2013Date of Patent: September 28, 2021Assignee: Sutherland Global Services, Inc.Inventors: Balamurugan Balasubramanian, Naveen Kumaresan, Sanooj P S, Venkatesh Madhavan
-
Publication number: 20150261598Abstract: A method for diagnosing and repairing a first computing device that is not able to be booted due to a malfunction of the first computing device is provided. The method comprises providing a boot tool stored on a removable computer readable storage medium; allowing the first computing device to be booted using the boot tool; providing for communication between the first computing device and a remote help desk computing device over a network; remotely identifying the malfunction of the first computing device; and pushing at least one repair data file from the remote help desk computing device to the first computing device or downloading the at least one repair data file from the Internet using the first computing device, wherein the at least one repair data file is configured for repairing the first computing device so that the first computing device is bootable without use of the boot tool.Type: ApplicationFiled: October 18, 2013Publication date: September 17, 2015Applicant: Sutherland Global Services, Inc.Inventors: Balamurugan Balasubramanian, Naveen Kumaresan, Sanooj P. S., Venkatesh Madhavan
-
Patent number: 8001497Abstract: Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.Type: GrantFiled: October 1, 2008Date of Patent: August 16, 2011Assignee: LSI CorporationInventors: Randall P. Fry, Balamurugan Balasubramanian, Kavitha Chaturvedula
-
Patent number: 7895546Abstract: A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.Type: GrantFiled: September 4, 2007Date of Patent: February 22, 2011Assignee: LSI CorporationInventors: Juergen K. Lahner, Balamurugan Balasubramanian, Kavitha Chaturvedula
-
Patent number: 7844929Abstract: A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.Type: GrantFiled: May 8, 2008Date of Patent: November 30, 2010Assignee: LSI CorporationInventors: Kavitha Chaturvedula, Juergen K. Lahner, Balamurugan Balasubramanian
-
Publication number: 20100217564Abstract: A method of physical simulation of an integrated circuit design comprising the steps of (A) reading design information for an integrated circuit from a computer readable storage medium, (B) reading library information and physical design information from the computer readable storage medium, (C) simulating the integrated circuit design based upon the library information and the physical design information using a computer, where the simulation of the integrated circuit design provides signoff accurate results and (D) determining whether the integrated circuit design meets one or more performance goals based upon results of the simulation of the integrated circuit design.Type: ApplicationFiled: February 26, 2009Publication date: August 26, 2010Inventors: Juergen K. Lahner, Balamurugan Balasubramanian, Kavitha Chaturvedula
-
Publication number: 20100083195Abstract: Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.Type: ApplicationFiled: October 1, 2008Publication date: April 1, 2010Applicant: LSI CORPORATIONInventors: Randall P. Fry, Balamurugan Balasubramanian, Kavitha Chaturvedula
-
Publication number: 20090282307Abstract: A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.Type: ApplicationFiled: May 8, 2008Publication date: November 12, 2009Inventors: Kavitha Chaturvedula, Juergen K. Lahner, Balamurugan Balasubramanian
-
Publication number: 20090063564Abstract: A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.Type: ApplicationFiled: September 4, 2007Publication date: March 5, 2009Inventors: Juergen K. Lahner, Balamurugan Balasubramanian, Kavitha Chaturvedula
-
Patent number: 7441210Abstract: A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in the file while the designer is editing the code to generate a plurality of characterization results and (C) generating a plurality of suggestions to the designer to modify the code based on a comparison of a plurality of goals for the circuit design and the characterization results.Type: GrantFiled: October 11, 2005Date of Patent: October 21, 2008Assignee: LSI CorporationInventors: Juergen K. Lahner, Juergen Dirks, Balamurugan Balasubramanian
-
Patent number: 7415687Abstract: A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.Type: GrantFiled: October 5, 2005Date of Patent: August 19, 2008Assignee: LSI CorporationInventors: Juergen K. Lahner, Balamurugan Balasubramanian, Randall P. Fry
-
Publication number: 20070083839Abstract: A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in the file while the designer is editing the code to generate a plurality of characterization results and (C) generating a plurality of suggestions to the designer to modify the code based on a comparison of a plurality of goals for the circuit design and the characterization results.Type: ApplicationFiled: October 11, 2005Publication date: April 12, 2007Inventors: Juergen Lahner, Juergen Dirks, Balamurugan Balasubramanian
-
Publication number: 20070079273Abstract: A method of placing and routing an integrated circuit design includes steps of (a) generating an initial placement and routing for at least a portion of an integrated circuit design; (b) analyzing the initial placement and routing of the integrated circuit design to find a critical location; (c) partitioning the initial placement and routing of the integrated circuit design into a series of nested shells wherein each shell surrounds the critical location and each preceding shell; (d) selecting an ordering of the shells; (e) selecting at least one of a timing constraint and an area constraint for each shell; and (f) placing and routing each shell in the order selected in step (d) according to the at least one timing constraint and area constraint selected in step (e).Type: ApplicationFiled: October 5, 2005Publication date: April 5, 2007Inventors: Juergen Lahner, Balamurugan Balasubramanian, Randall Fry
-
Publication number: 20070079266Abstract: A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving as input an integrated circuit design and a set of design rules, analyzing the integrated circuit design to identify design rule violations, and generating as output a compilation of each of the design rule violations and a corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Inventors: Krishna Devineni, Juergen Lahner, Gregory Pierce, Balamurugan Balasubramanian, Srinivas Adusumalli, Kiran Atmakuri, Kavitha Chaturvedula, Randall Fry
-
Patent number: 7082584Abstract: A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.Type: GrantFiled: April 30, 2003Date of Patent: July 25, 2006Assignee: LSI Logic CorporationInventors: Juergen Lahner, Kiran Atmakuri, Kavitha Chaturvedula, Balamurugan Balasubramanian, Krishna Devineni, Srinivas Adusumalli, Randall P. Fry, Gregory A. Pierce
-
Patent number: 6990651Abstract: An integrated circuit design library includes a timing parameter representative of a design element in an integrated circuit; an area size parameter representative of the design element in an integrated circuit; and a routing demand parameter representative of a number of connections required for the design element for each value of the timing parameter and the area size parameter.Type: GrantFiled: May 14, 2003Date of Patent: January 24, 2006Assignee: LSI Logic CorporationInventors: Balamurugan Balasubramanian, Juergen Lahner, Srinivas Adusumalli
-
Patent number: 6907588Abstract: A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor plan, computing routing demand numbers for the regions in the floor plan, computing routing resource numbers for the regions in the floor plan, and generating a congestion estimate of the register transfer level code as a function of the routing demand numbers and the routing resource numbers.Type: GrantFiled: December 31, 2002Date of Patent: June 14, 2005Assignee: LSI Logic CorporationInventors: Balamurugan Balasubramanian, Juergen Lahner, Srinivas Adusumalli
-
Publication number: 20040230919Abstract: An integrated circuit design library includes a timing parameter representative of a design element in an integrated circuit; an area size parameter representative of the design element in an integrated circuit; and a routing demand parameter representative of a number of connections required for the design element for each value of the timing parameter and the area size parameter.Type: ApplicationFiled: May 14, 2003Publication date: November 18, 2004Inventors: Balamurugan Balasubramanian, Juergen Lahner, Srinivas Adusumalli
-
Publication number: 20040221249Abstract: A method of automatically analyzing RTL code includes steps for receiving as input RTL code for an integrated circuit design, selecting an RTL platform incorporating circuit design rules for a vendor of the integrated circuit design, displaying the design rules from the RTL platform on a graphic user interface, selecting a number of the design rules from the graphic user interface, performing an analysis in the RTL platform of the RTL code for each of the selected design rules, and generating as output a result of the analysis for each of the selected design rules.Type: ApplicationFiled: April 30, 2003Publication date: November 4, 2004Inventors: Juergen Lahner, Kiran Atmakuri, Kavitha Chaturvedula, Balamurugan Balasubramanian, Krishna Devineni, Srinivas Adusumalli, Randall P. Fry, Gregory A. Pierce