Patents by Inventor Balamurugan Balasubramanian

Balamurugan Balasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LENGTH MATRIX GENERATOR FOR REGISTER TRANSFER LEVEL CODE
    Publication number: 20040128640
    Abstract: A method of generating a length matrix for register transfer level code includes steps for receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a user defined hierarchical depth; mapping the register transfer level code to a design library, generating a connectivity matrix for the plurality of compile units, generating a priority list of interconnections from the connectivity matrix, generating placement coordinates for the compile units from the priority list of interconnections and the connectivity matrix, and generating as output at least one of the connectivity matrix and the placement coordinates.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Srinivas Adusumalli, Juergen Lahner, Balamurugan Balasubramanian
  • Congestion estimation for register transfer level code
    Publication number: 20040128639
    Abstract: A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor plan, computing routing demand numbers for the regions in the floor plan, computing routing resource numbers for the regions in the floor plan, and generating a congestion estimate of the register transfer level code as a function of the routing demand numbers and the routing resource numbers.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Applicant: LSI Logic Corporation
    Inventors: Balamurugan Balasubramanian, Juergen Lahner, Srinivas Adusumalli
  • Length matrix generator for register transfer level code
    Patent number: 6757885
    Abstract: A method of generating a length matrix for register transfer level code includes steps for receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a user defined hierarchical depth; mapping the register transfer level code to a design library, generating a connectivity matrix for the plurality of compile units, generating a priority list of interconnections from the connectivity matrix, generating placement coordinates for the compile units from the priority list of interconnections and the connectivity matrix, and generating as output at least one of the connectivity matrix and the placement coordinates.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: June 29, 2004
    Assignee: LSI Logic Corporation
    Inventors: Srinivas Adusumalli, Juergen Lahner, Balamurugan Balasubramanian