Patents by Inventor Balamurugan Subramanian
Balamurugan Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10388609Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.Type: GrantFiled: November 25, 2015Date of Patent: August 20, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
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Publication number: 20160141251Abstract: Embodiments of the invention provide a semiconductor wafer with information for detecting a die attach pick error on the semiconductor wafer. The semiconductor wafer has a plurality of electrical chips. The semiconductor wafer also has a die map with a plurality of locations of a set of pre-selected check good electrical chips (CGEC) die from the plurality of electrical chips on the semiconductor wafer and flat edge orientation marker. A reference feature located in a predetermined area of the semiconductor wafer. A reference die is located in a known spatial relationship to the reference feature. The die map is defined relative to the location of the reference die on the semiconductor wafer.Type: ApplicationFiled: November 25, 2015Publication date: May 19, 2016Inventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
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Patent number: 9229058Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.Type: GrantFiled: June 25, 2013Date of Patent: January 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
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Publication number: 20140180949Abstract: A system and method for automated coding and testing of insurance benefits is provided. The system comprises a user interface to receive data pertaining to benefits based on insurance benefits contracts and to create Benefit Plan Designs (BPDs) using the received data. The system further comprises a benefits mapping module to map the benefits from the BPDs with pre-stored benefits in a repository. Further, the system comprises a benefit code translator to translate the mapped benefits into codes or mnemonics and a benefit code updating engine to update the codes or mnemonics into one or more claims platforms. In addition, the system comprises a test scenario mapping module to generate test claims and expected results and to execute the generated test claims on the one or more claims platforms to generate actual test results. The system also comprises a validation engine to validate the codes or mnemonics.Type: ApplicationFiled: March 12, 2013Publication date: June 26, 2014Applicant: COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT. LTD.Inventors: Paramesh Ramasamy, Janakiraman Radhakrishnan, Balamurugan Subramanian, Gunasekaran Ramasamy, Sankar Kasilingam, Gurumurthy Harikrishnan, Gopi Krishnappa
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Publication number: 20140002128Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.Type: ApplicationFiled: June 25, 2013Publication date: January 2, 2014Inventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
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Publication number: 20130214388Abstract: A semiconductor wafer is adapted to support partial wafer processing generally transparently to a facility capable of processing a full wafer. The wafer has provided thereon a plurality of semiconductor dice and a plurality of visible reference features. The reference features are positioned among the dice to support a predetermined partitioning of the wafer into partial wafers. The positioning of the reference features may render each partial wafer uniquely visually distinguishable from every other partial wafer. Each partial wafer may contain at least one of the reference features, with the position of each reference feature identified in accordance with a coordinate system of an electronic wafer map. The positioning of the reference features may provide a visual indication of where to cut the wafer to effect the partitioning.Type: ApplicationFiled: February 20, 2012Publication date: August 22, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Balamurugan Subramanian
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Patent number: 7915087Abstract: In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle pattern (602) that is configured by arranging the dies in an array having m rows and n columns, where the m rows start in a row adjacent to the orientation marker (606), and m and n are integers. The reticle pattern (602) is transferred to the full wafer (600) to sequentially form a portion of the dies. The transferring includes placing an inkless marker (620) in the form of one or more non-circuit dies between the n columns of adjacent reticle patterns. The reticle pattern (602) is repeatedly transferred to form a remaining portion of the dies to complete the full wafer (600). A wafer map for the full wafer (600) is stored, with the wafer map including a non-circuit bin containing data describing the inkless marker (620).Type: GrantFiled: April 6, 2009Date of Patent: March 29, 2011Assignee: Texas Instruments IncorporatedInventor: Balamurugan Subramanian
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Publication number: 20090191689Abstract: In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle pattern (602) that is configured by arranging the dies in an array having m rows and n columns, where the m rows start in a row adjacent to the orientation marker (606), and m and n are integers. The reticle pattern (602) is transferred to the full wafer (600) to sequentially form a portion of the dies. The transferring includes placing an inkless marker (620) in the form of one or more non-circuit dies between the n columns of adjacent reticle patterns. The reticle pattern (602) is repeatedly transferred to form a remaining portion of the dies to complete the full wafer (600). A wafer map for the full wafer (600) is stored, with the wafer map including a non-circuit bin containing data describing the inkless marker (620).Type: ApplicationFiled: April 6, 2009Publication date: July 30, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Balamurugan SUBRAMANIAN
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Patent number: 7534655Abstract: In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle pattern (602) that is configured by arranging the dies in an array having m rows and n columns, where the m rows start in a row adjacent to the orientation marker (606), and m and n are integers. The reticle pattern (602) is transferred to the full wafer (600) to sequentially form a portion of the dies. The transferring includes placing an inkless marker (620) in the form of one or more non-circuit dies between the n columns of adjacent reticle patterns. The reticle pattern (602) is repeatedly transferred to form a remaining portion of the dies to complete the full wafer (600). A wafer map for the full wafer (600) is stored, with the wafer map including a non-circuit bin containing data describing the inkless marker (620).Type: GrantFiled: October 10, 2006Date of Patent: May 19, 2009Assignee: Texas Instruments IncorporatedInventor: Balamurugan Subramanian
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Publication number: 20080085588Abstract: In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle pattern (602) that is configured by arranging the dies in an array having m rows and n columns, where the m rows start in a row adjacent to the orientation marker (606), and m and n are integers. The reticle pattern (602) is transferred to the full wafer (600) to sequentially form a portion of the dies. The transferring includes placing an inkless marker (620) in the form of one or more non-circuit dies between the n columns of adjacent reticle patterns. The reticle pattern (602) is repeatedly transferred to form a remaining portion of the dies to complete the full wafer (600). A wafer map for the full wafer (600) is stored, with the wafer map including a non-circuit bin containing data describing the inkless marker (620).Type: ApplicationFiled: October 10, 2006Publication date: April 10, 2008Applicant: Texas Instruments IncorporatedInventor: Balamurugan Subramanian
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Patent number: 7015068Abstract: A method of processing a partial wafer in accordance with one embodiment comprises includes after of loading partial wafer into wafer table of pick and place equipment after saw; downloading wafer map data for the wafer from wafer map data host. If the partial wafer has a reference die then positioning the wafer table to the reference die and then moving the wafer table to the last column of the partial wafer. If the partial wafer does not have a reference die the last column (LCOLUMN) information is obtained from wafer map data header field in one embodiment and using LCOLUMN information remove all dies in the right side of partial wafer map. The wafer table is moved to pseudo reference die which is the first die in the bottom right. The pseudo reference die coordinate (x1, y1) is calculated where x1=first column from right to left that has a die in the wafer map data and y1=first bottom most row in the column x1 from the wafer map data.Type: GrantFiled: June 3, 2002Date of Patent: March 21, 2006Assignee: Texas Instruments IncorporatedInventor: Balamurugan Subramanian
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Patent number: 6927081Abstract: A method of blind assembly processing a wafer by pick and place equipment is described. This method includes determining the wafer diameter or radius and determining the bad die edge exclusive zone. This determined diameter or radius and the determined edge exclusive zone is used to make a black paper mask and place it over the wafer or to cut or saw away from the wafer the bad die edge exclusive zone. This enables the pick and place equipment to avoid the bad dies in the bad die edge exclusive zone.Type: GrantFiled: April 24, 2003Date of Patent: August 9, 2005Assignee: Texas Instruments IncorporatedInventors: Balamurugan Subramanian, Sreenivasan K. Koduri
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Patent number: 6821866Abstract: A tool and method is described to decide partial wafer sizes to process multiple random sizes of wafers in pick and place equipment for wafermap operation. The tool identifies the wafer and gets wafermap data. The position of one or more cutters is displayed. The position of the cutters relative to the wafer is displayed. The tool generates and displaying the results of the type of dies in each partial that would result from a cut according to said displayed position of the cutters.Type: GrantFiled: March 11, 2003Date of Patent: November 23, 2004Assignee: Texas Instruments IncorporatedInventor: Balamurugan Subramanian
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Publication number: 20040215417Abstract: A method of blind assembly processing a wafer by pick and place equipment is described. This method includes determining the wafer diameter or radius and determining the bad die edge exclusive zone. This determined diameter or radius and the determined edge exclusive zone is used to make a black paper mask and place it over the wafer or to cut or saw away from the wafer the bad die edge exclusive zone. This enables the pick and place equipment to avoid the bad dies in the bad die edge exclusive zone.Type: ApplicationFiled: April 24, 2003Publication date: October 28, 2004Inventors: Balamurugan Subramanian, Sreenivasan K. Koduri
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Publication number: 20040180513Abstract: A tool and method is described to decide partial wafer sizes to process multiple random sizes of wafers in pick and place equipment for wafermap operation. The tool identifies the wafer and gets wafermap data. The position of one or more cutters is displayed. The position of the cutters relative to the wafer is displayed. The tool generates and displaying the results of the type of dies in each partial that would result from a cut according to said displayed position of the cutters.Type: ApplicationFiled: March 11, 2003Publication date: September 16, 2004Inventor: Balamurugan Subramanian
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Patent number: 6756796Abstract: An improved method for pick and place equipment operation is provided by an improved method for identifying the reference die on a wafer. A recording of good die, partial die, mirror die, and partial mirror die information about the neighboring dies about the reference die is formed by recording step is performed by starting at the reference die and moving clockwise about the reference die one die at a time to form a stored neighborhood matrix. Searching and identifying the reference die on a wafer includes aligning the wafer table with a wafer thereon at the reference die location coordinates determined by the recording step and starting at this location moving the wafer table one die at a time about the aligned reference die recording the neighboring die or partial die as full good die, partial die, mirror die, or partial mirror die and comparing to the information about dies or partial dies neighboring said reference die to identify the reference die.Type: GrantFiled: August 9, 2002Date of Patent: June 29, 2004Assignee: Texas Instruments IncorporatedInventor: Balamurugan Subramanian
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Publication number: 20040029306Abstract: An improved method for pick and place equipment operation is provided by an improved method for identifying the reference die on a wafer. A recording of good die, partial die, mirror die, and partial mirror die information about the neighboring dies about the reference die is formed by recording step is performed by starting at the reference die and moving clockwise about the reference die one die at a time to form a stored neighborhood matrix. Searching and identifying the reference die on a wafer includes aligning the wafer table with a wafer thereon at the reference die location coordinates determined by the recording step and starting at this location moving the wafer table one die at a time about the aligned reference die recording the neighboring die or partial die as full good die, partial die, mirror die, or partial mirror die and comparing to the information about dies or partial dies neighboring said reference die to identify the reference die.Type: ApplicationFiled: August 9, 2002Publication date: February 12, 2004Inventor: Balamurugan Subramanian
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Publication number: 20030224552Abstract: A method of processing a partial wafer in accordance with one embodiment comprises includes after of loading partial wafer into wafer table of pick and place equipment after saw; downloading wafer map data for the wafer from wafer map data host. If the partial wafer has a reference die then positioning the wafer table to the reference die and then moving the wafer table to the last column of the partial wafer. If the partial wafer does not have a reference die the last column (LCOLUMN) information is obtained from wafer map data header field in one embodiment and using LCOLUMN information remove all dies in the right side of partial wafer map. The wafer table is moved to pseudo reference die which is the first die in the bottom right. The pseudo reference die coordinate (x1, y1) is calculated where x1=first column from right to left that has a die in the wafer map data and y1=first bottom most row in the column x1 from the wafer map data.Type: ApplicationFiled: June 3, 2002Publication date: December 4, 2003Inventor: Balamurugan Subramanian
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Publication number: 20030220706Abstract: A wafer map host system and methodology that supports the use of and manipulation of wafer map information for multiple semiconductor processes is disclosed. The system includes a database for storing wafer maps; an interface for providing interfaces to a plurality of wafer manufacturing processes and/or equipment; and a wafer map processor coupled between said database and said interface for managing relationships of various tasks during a wafer map data transaction between the processes and/or equipment and the database. The tasks include deciding which wafer map is required, which equipment is involved, what is the manufacturing flow being used, how to re-map the various bin assignments considering the next manufacturing process, and merging two or more wafer map data for the next manufacturing process.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventors: Elmer M. Abenes, Balamurugan Subramanian, James R. Calles
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Patent number: 6380000Abstract: An automatic recovery method for a Die Bonder Wafer Table in the event of loss of wafermap coordinate data is provided. If after moving to the first map die position and there is no die, the wafer table is moved back one die position in the direction of the track from the reference die to the first map die and then the closest coordinate from the map data of current bin in reverse direction is found and the table is moved to that position. If there is alignment fail or no die, the same step of moving back and finding the closest die coordinate from the map data in reverse direction and moving to that position is repeated. Otherwise, the next die coordinate from the map data of the current bin in reverse direction towards the first map die is found and the table is moved to this die coordinate position. The table is moved to the next die position in the forward direction if alignment fails or no die is encountered.Type: GrantFiled: September 22, 2000Date of Patent: April 30, 2002Assignee: Texas Instruments IncorporatedInventor: Balamurugan Subramanian