Abstract: Aspects of the invention include tracking relative ages of instructions in a first-in-first-out (FIFO) issue queue of an out-of-order (OoO) processor. The FIFO issue queue is configured to add instructions to the issue queue in a sequential order and to remove instructions from the issue queue in any order including a non-sequential order. The tracking of relative ages of instructions includes maintaining a head pointer to a location of an oldest instruction in the issue queue and a tail pointer to a location of a last instruction added to the issue queue. It is determined periodically whether the tail pointer is pointing to a location that includes a valid instruction. The tail pointer is updated to point to a previous sequential location in the issue queue based at least in part on determining that the tail pointer is not pointing to a location that corresponds to a valid instruction.

Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions in a group of instructions in the issue queue that were added to the issue queue prior to the instruction and that are not included in the threshold number of instructions that are tracked individually. A dependency between the instruction and the one or more other instructions in the group of instructions is tracked using a single summary bit that is set to indicate that a dependency exists between the instruction and the group of instructions. Instructions are issued from the issue queue based at least in part on the tracking.

Abstract: Aspects of the invention include tracking relative ages of instructions in an issue queue of an OoO processor. The tracking includes grouping entries in the issue queue into a pool of blocks, each block containing two or more entries that are configured to be allocated and deallocated as a single unit, each entry configured to store an instruction. Blocks are selected in any order from the pool of block for allocation. The selected blocks are allocated and the relative ages of the allocated blocks are tracked based at least in part on an order that the blocks are allocated. Each allocated block is configured as a first-in-first-out (FIFO) queue of entries, configured to add instructions to the block in a sequential order, and configured to remove instructions from the block in any order including a non-sequential order. The relative ages of instructions within each allocated block are tracked.

Abstract: Aspects of the invention include buffered instruction dispatching to an issue queue. A non-limiting example includes dispatching from a dispatch unit of a processor a first group of instructions selected from a first plurality of instructions to a first issue queue partition of the processor in a first cycle. A second group of instructions selected from the first plurality of instructions is passed to an issue queue buffer of the processor in the first cycle. The second group of instructions is passed from the issue queue buffer to the first issue queue partition in a second cycle. A third group of instructions selected from a second plurality of instructions is dispatched to a second issue queue partition in the second cycle.

Abstract: Aspects include monitoring a number of instructions of a first type dispatched to a first shared port of an issue queue of a processor and determining whether the number of instructions of the first type dispatched to the first shared port exceeds a port selection threshold. An instruction of a third type is dispatched to a second shared port of the issue queue associated with a plurality of instructions of a second type based on determining that the number of instructions of the first type dispatched to the first shared port exceeds the port selection threshold. The instruction of the third type is dispatched to the first shared port of the issue queue associated with a plurality of instructions of the first type based on determining that the number of instructions of the first type dispatched to the first shared port does not exceed the port selection threshold.

Abstract: Embodiments for implementing a fused multiply-multiply-accumulate (“FMMA”) unit by one or more processors in a computing system. Mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two product having a larger exponent may be determined in parallel. The addend may be aligned relative to the alternative product having the larger exponent. The product having the smallest exponent may be aligned relative to the alternative product having the larger exponent according to the alignment shift amount.

Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, tracking a specific dependency on each of a threshold number of instructions most recently added to the issue queue prior to the instruction, tracking as a single group a dependency of the instruction on any instructions in the issue queue that are not in the threshold number of instructions, and tracking for each source register used by the instruction an indicator of whether its content is dependent on results from an instruction in the single group that has not finished execution. Based at least in part on detecting removal from the issue queue of an instruction in the single group that has issued and not finished execution, the method includes indicating that the instruction is ready for issuance or waiting for a notification that the removed instruction has finished execution.

Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.

Abstract: A non-limiting example of a computer-implemented method for implementing wide vector execution for an out-of-order processor includes entering, by the out-of-order processor, a single thread mode. The method further includes partitioning, by the out-of-order processor, a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit. The method further includes receiving, by a vector scalar register of the out-of-order processor, a wide vector instruction. The method further includes processing, by the wide vector execution unit, the wide vector instruction.

Abstract: A non-limiting example of a computer-implemented method for implementing wide vector execution for an out-of-order processor includes entering, by the out-of-order processor, a single thread mode. The method further includes partitioning, by the out-of-order processor, a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit. The method further includes receiving, by a vector scalar register of the out-of-order processor, a wide vector instruction. The method further includes processing, by the wide vector execution unit, the wide vector instruction.

Abstract: Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.

Abstract: Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.

Abstract: Embodiments of the present invention include methods, systems, and computer program products for allocating and deallocating reorder queue entries for an out-of-order (OoO) processor. An example method includes dividing the reorder queue into a plurality of regions to store reorder queue entries; allocating a plurality of reorder queue entries into an instruction tag array for tracking the reorder queue entries based at least in part on an associated instruction tag; loading instruction tags into each region of the plurality of regions beginning with a first region of the plurality of regions, wherein a first plurality of instruction tags is loaded into the first region; deallocating all of the first plurality of instruction tags of the first region; and subsequent to all of the instruction tags of the first region being deallocated, loading a second plurality of instruction tags to the first region of the plurality of regions.

Abstract: Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.

Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit. An example method includes looking up, by a load-store unit (LSU), an entry in an effective address directory (EAD) for an effective address (EA) of an operand of an instruction to be launched. Further, the method includes, in response to the EA being present in the EAD, launching, by the LSU, the instruction with the RA from the EAD, and in response to the EA not being present in the EAD, looking up, by the LSU, the EA in an effective real table (ERT) entry, and launching the instruction with the RA from the ERT entry. Further, in response to the ERT entry to be removed, the ERT entry including an ERT index and a mapping between the EA and the RA, removing the entry of the EA from the EAD.

Abstract: Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.

Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit. An example method includes looking up, by a load-store unit (LSU), an entry in an effective address directory (EAD) for an effective address (EA) of an operand of an instruction to be launched. Further, the method includes, in response to the EA being present in the EAD, launching, by the LSU, the instruction with the RA from the EAD, and in response to the EA not being present in the EAD, looking up, by the LSU, the EA in an effective real table (ERT) entry, and launching the instruction with the RA from the ERT entry. Further, in response to the ERT entry to be removed, the ERT entry including an ERT index and a mapping between the EA and the RA, removing the entry of the EA from the EAD.

Abstract: Aspects of the invention include a computer-implemented method for executing one or more instructions by a processing unit. The method includes receiving, by an instruction fetch unit (IFU), a request to fetch an instruction for execution, wherein the instruction includes an effective address (EA). The IFU can further access an instruction cache directory (I-directory) using the EA of the requested instruction to determine whether the EA of the requested instruction matches an EA stored in an associated instruction cache (I-cache). An instruction cache (I-cache) can output the requested instruction in response to or based at least in part on determining that the requested instruction EA matches an entry in the I-cache. A decode unit can decode the requested instruction output by the I-cache.

Abstract: Technical solutions are described for executing one or more out-of-order (OoO) instructions by a processing unit. The execution includes detecting, by a load-store unit (LSU), a load-hit-store (LHS) in an out-of-order execution of the instructions, the detecting based only on effective addresses. The detecting includes determining an effective address associated with an operand of a load instruction. The detecting further includes determining whether a store instruction entry using said effective address to store a data value is present in a store reorder queue, and indicating that an LHS has been detected based at least in part on determining that store instruction entry using said effective address is present in the store reorder queue. In response to detecting the LHS, a store forwarding is performed that includes forwarding data from the store instruction to the load instruction.