Abstract: Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window. The issuing includes, in response to determining a first effective address (EA) being used by a first instruction, the first EA corresponding to a first real address (RA), creating a first effective real translation (ERT) table entry in an ERT table, the ERT entry mapping the first EA to the first RA. Further, in response to determining an EA synonym used by a second instruction, the execution includes replacing the first ERT entry with a second ERT entry, wherein the second ERT entry maps the second EA with the first RA, and creating an ERT eviction (ERTE) table entry in an ERTE table, wherein the ERTE entry maps the first RA to the first EA, the ERTE table entry maintains the relationship between the first EA and the first RA.

Abstract: Aspects of the invention include detecting, in an out-of-order (OoO) processor, that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is the oldest group in an entry of a global completion table (GCT). It is determined that the entry in the GCT is a merged entry that is associated with both the first group of in-flight instructions and a second group of in-flight instructions dispatched immediately subsequent to the first group of in-flight instructions. The first group of in-flight instructions and the second group of in-flight instructions are completed in a single processor cycle. The completing is based at least in part on detecting that all instructions in the first group of in-flight instructions have a status of finished. The completing includes requesting release of resources utilized by both the first and second groups of in-flight instructions.

Abstract: Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window. The issuing includes, in response to determining a first effective address (EA) being used by a first instruction, the first EA corresponding to a first real address (RA), creating a first effective real translation (ERT) table entry in an ERT table, the ERT entry mapping the first EA to the first RA. Further, in response to determining an EA synonym used by a second instruction, the execution includes replacing the first ERT entry with a second ERT entry, wherein the second ERT entry maps the second EA with the first RA, and creating an ERT eviction (ERTE) table entry in an ERTE table, wherein the ERTE entry maps the first RA to the first EA, the ERTE table entry maintains the relationship between the first EA and the first RA.

Abstract: Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions. A dependency between the instruction and each of the other instructions is tracked as a plurality of groups by indicating that a dependency exists between the instruction and one of the groups based on identifying a dependency between the instruction and at least one instruction in the group. Instructions are issued from the issue queue based at least in part on the tracking.

Abstract: Technical solutions are described for executing one or more out-of-order instructions by a load-store unit (LSU) by detecting a load-hit-load (LHL) case based only on effective addresses (EA). An example method includes, in response to receiving a first load instruction, creating an entry in a LHL table. Further, in response to receiving a second load instruction in the load reorder queue, and in response to the predetermined number of bits from a second EA used by the second load instruction matching the predetermined number of bits from the first EA, comparing the first EA and the second EA. Further, a first thread identifier for the first load instruction is compared with a second thread identifier for the second load instruction. In response to the first EA matching the second EA, and the first thread identifier matching the second thread identifier, the method includes flushing the first load instruction.

Abstract: Provided are methods, systems, and computer program products to implementing a split store data queue for an out-of-order (OoO) processor. A non-limiting example of the computer-implemented method includes detecting, by the OoO processor, a mode of the OoO processor. The method further includes partitioning, by the OoO processor, a first store data queue (SDQ) and a second SDQ based at least in part on the mode of the OoO processor. The method further includes receiving, by the OoO processor, a vector operand. The method further includes storing, by the OoO processor, the vector operand in at least one of the first SDQ and the second SDQ based at least in part on the mode of the OoO processor.

Abstract: Technical solutions are described for hazard detection of out-of-order execution of load and store instructions without using real addresses in a processing unit. An example includes an out-of-order load-store unit (LSU) for transferring data between memory and registers. The LSU detects a store-hit-load (SHL) in an out-of-order execution of instructions based only on effective addresses by: determining an effective address associated with a store instruction; determining whether a load instruction entry using said effective address is present in a load reorder queue; and indicating that a SHL has been detected based at least in part on determining that load instruction entry using said effective address is present in the load reorder queue. The LSU, in response to detecting the SHL, flushes instructions starting from a load instruction corresponding to the load instruction entry.

Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.

Abstract: Technical solutions are described for hazard detection of out-of-order execution of load and store instructions without using real addresses in a processing unit. An example includes an out-of-order load-store unit (LSU) for transferring data between memory and registers. The LSU detects a store-hit-load (SHL) in an out-of-order execution of instructions based only on effective addresses by: determining an effective address associated with a store instruction; determining whether a load instruction entry using said effective address is present in a load reorder queue; and indicating that a SHL has been detected based at least in part on determining that load instruction entry using said effective address is present in the load reorder queue. The LSU, in response to detecting the SHL, flushes instructions starting from a load instruction corresponding to the load instruction entry.

Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.

Abstract: Aspects of the invention include a computer-implemented method for executing one or more instructions by a processing unit. The method includes fetching, by an instruction fetch unit, a first instruction from an instruction cache. The method further includes associating, by an effective address table logic, an entry in an effective address table (EAT) with the first instruction. The method further includes fetching, by the instruction fetch unit, a second instruction from the instruction cache, wherein the first instruction occurs before a branch has been taken and the second instruction occurs after the branch has been taken. The method further includes associating at least a portion of the entry in the EAT associated with the first instruction in response to the second instruction utilizing a cache line utilized by the first instruction and processing the first instruction and the second instruction through a processor pipeline utilizing the entry of the EAT.

Abstract: Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a load-store unit (LSU), instructions from an out-of-order (OoO) window. The OoO execution includes determining an effective address being used by a load instruction from the OoO window. Further, the execution includes determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT). In response to the effective address being present in the EAD, the execution includes accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address, and issuing the load instruction using the real address from the corresponding ERT entry.

Abstract: Aspects of the invention include receiving, by a processor, a plurality of instructions at an instruction pipeline. The processor can further determine an operand bit field size for each of the received plurality of instructions. The processor can further compare the operand bit field size of at least a subset of the received instructions to a predetermined threshold. The processor can further fuse at least two of the received instructions that have an operand bit field size that meets the predetermined threshold. The processor can further perform an execution stage within the instruction pipeline to execute the received instructions, including the fused instructions.

Abstract: Embodiments of the present invention include methods, systems, and computer program products for implementing instruction fusion after register rename. A computer-implemented method includes receiving, by a processor, a plurality of instructions at an instruction pipeline. The processor can further performing a register rename within the instruction pipeline in response to the received plurality of instructions. The processor can further determine that two or more of the plurality of instructions can be fused after the register rename. The processor can further fuse the two or more instructions that can be fused based on the determination to create one or more fused instructions. The processor can further perform an execution stage within the instruction pipeline to execute the plurality of instructions, including the one or more fused instructions.

Abstract: Aspects of the invention include a computer-implemented method for executing one or more instructions by a processing unit. The method includes receiving, by an instruction fetch unit (IFU), a request to fetch an instruction for execution, wherein the instruction includes an effective address (EA). The IFU can further access an instruction cache directory (I-directory) using the EA of the requested instruction to determine whether the EA of the requested instruction matches an EA stored in an associated instruction cache (I-cache). An instruction cache (I-cache) can output the requested instruction in response to or based at least in part on determining that the requested instruction EA matches an entry in the I-cache. A decode unit can decode the requested instruction output by the I-cache.

Abstract: Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a load-store unit (LSU), instructions from an out-of-order (OoO) window. The OoO execution includes determining an effective address being used by a load instruction from the OoO window. Further, the execution includes determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT). In response to the effective address being present in the EAD, the execution includes accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address, and issuing the load instruction using the real address from the corresponding ERT entry.

Abstract: Aspects of the invention include detecting, in an out-of-order (OoO) processor, that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is the oldest group in an entry of a global completion table (GCT). It is determined that the entry in the GCT is a merged entry that is associated with both the first group of in-flight instructions and a second group of in-flight instructions dispatched immediately subsequent to the first group of in-flight instructions. The first group of in-flight instructions and the second group of in-flight instructions are completed in a single processor cycle. The completing is based at least in part on detecting that all instructions in the first group of in-flight instructions have a status of finished. The completing includes requesting release of resources utilized by both the first and second groups of in-flight instructions.

Abstract: Aspects of the invention include tracking relative ages of instructions in a first-in-first-out (FIFO) issue queue of an out-of-order (OoO) processor. The FIFO issue queue is configured to add instructions to the issue queue in a sequential order and to remove instructions from the issue queue in any order including a non-sequential order. The tracking of relative ages of instructions includes maintaining a head pointer to a location of an oldest instruction in the issue queue and a tail pointer to a location of a last instruction added to the issue queue. It is determined periodically whether the tail pointer is pointing to a location that includes a valid instruction. The tail pointer is updated to point to a previous sequential location in the issue queue based at least in part on determining that the tail pointer is not pointing to a location that corresponds to a valid instruction.

Abstract: Aspects of the invention include tracking relative ages of instructions in an issue queue of an OoO processor. The tracking includes grouping entries in the issue queue into a pool of blocks, each block containing two or more entries that are configured to be allocated and deallocated as a single unit, each entry configured to store an instruction. Blocks are selected in any order from the pool of block for allocation. The selected blocks are allocated and the relative ages of the allocated blocks are tracked based at least in part on an order that the blocks are allocated. Each allocated block is configured as a first-in-first-out (FIFO) queue of entries, configured to add instructions to the block in a sequential order, and configured to remove instructions from the block in any order including a non-sequential order. The relative ages of instructions within each allocated block are tracked.