Abstract: A method for securely sharing of data by an electronic device is provided. The method includes receiving, by the electronic device, data associated with the at least one application available at the electronic device and obtaining, by the electronic device, secured data by transforming the data associated with at least one application into an unrecognizable format using at least one conceal factor and at least one noise input. Further, the method includes extracting, by the electronic device, a plurality of features from the secured data, and sharing, by the electronic device, the plurality of features extracted from the secured data to a plurality of servers.

Abstract: Embodiments herein provide a method for securing Neural Network (NN) models. The method includes: identifying, by the first electronic device, a crucial layer of a first NN model that is to be deployed for processing in a second electronic device. The method includes extracting, by the first electronic device, the crucial layer of the first NN model. The method includes encrypting, by the first electronic device, the crucial layer. The method includes generating, by the first electronic device, a second NN model includes the encrypted crucial layer. The method includes deploying, by the first electronic device, the second NN model to the second electronic device for processing in the second electronic device.

Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

Abstract: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT.

Abstract: A circuit for measuring maximum operating frequency and its corresponding duty cycle for an input I/O cell implementation under test (IUT) includes a condition checking module, a central control module and a duty cycle measurement module. The condition checking module checks an upper threshold voltage and a lower threshold voltage. The central control module controls a plurality of operations for measuring the frequency. The duty cycle measurement module measures the duty cycle and finally all these modules together and calculates maximum operating frequency of the IUT.

Abstract: A process for the complete destruction of gelled sulphur mustard (SM), comprising the steps of: (a) dissolving gelled sulphur mustard (SM) in organic solvent such as 2-chloroethanol, methanol, methyl cellosolve or mixtures of these to obtain a clear mixture, (b) incinerating the clear gelled sulphur mustard solvent mixture obtained from step (a); (c) dissolving residual gelled SM obtained from step (c) into non-toxic products; (d) chemically converting dissolved SM obtained from step (c) into non-toxic products.

Abstract: A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.

Abstract: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT.

Abstract: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT.

Abstract: An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data bits, a wrapper for converting the memory into a first-in first-out (FIFO) memory, and a controller for performing operations on the memory. In operation, the memory is converted into a FIFO memory after storing data, and output logic selects data to be output in a serial manner.

Abstract: An optical tracking assembly for an optical mouse includes a light source, an optical sensor chip, and an integral optics assembly. The integral optics assembly includes lenses and alignment features receiving the light source. The alignment features center the light source to the lenses and control a distance the light source is placed away from a navigation surface that reflects light onto the optical sensor chip. The lenses may include (1) collimating lenses for collimating light from the light source along a first optical axis to the navigation surface, and (2) imaging lenses for imaging reflected light from the navigation surface along a second optical axis to the optical sensor chip.

Abstract: An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localized Signal Generators located inside each memory block and controlled by said Centralized Flow Controller for applying specified test patterns on the associated memory array.

Abstract: A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.

Abstract: A circuit for measuring maximum operating frequency and its corresponding duty cycle for an input I/O cell implementation under test (IUT) includes a condition checking module, a central control module and a duty cycle measurement module. The condition checking module checks an upper threshold voltage and a lower threshold voltage. The central control module controls a plurality of operations for measuring the frequency. The duty cycle measurement module measures the duty cycle and finally all these modules together and calculates maximum operating frequency of the IUT.

Abstract: A configurable length first-in first-out (FIFO) memory includes a memory core for storing data, a write address counter connected to the memory core for counting locations for writing the data to be stored, and a read address counter connected to the memory core for counting the locations for reading the stored data. The read address counter includes a comparator for generating a synchronous reset for itself. A selector is connected to the comparator for selecting a user defined FIFO length, or a pre-programmed write address counter length.

Abstract: A compact and miniature optical navigation device integrates an illumination channel and an imaging channel into single piece. The present invention integrates the optical system, the mechanical system, and the electrical system into a small form factor device. The compact and miniature optical navigation device includes a photo-imaging element, a housing, and a first substrate. The photo-imaging element comprises an imaging channel and an illumination channel. The housing includes an aperture stop and an alignment element. The aperture stop and the housing are integrated into one piece and the alignment element is part of the housing. The first substrate includes a light source and a sensor. The light source and the sensor are located on the same surface of the first substrate. The light emitted from the light source passes through the illumination channel, reflected from the navigating surface and forms the image on the sensor.

Abstract: An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.