Patents by Inventor Baofu Zhu

Baofu Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210234045
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.
    Type: Application
    Filed: January 24, 2020
    Publication date: July 29, 2021
    Inventors: Arkadiusz Malinowski, Baofu Zhu, Judson R. Holt, Shiv Kumar Mishra
  • Publication number: 20210233999
    Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Ali Razavieh, Julien Frougier
  • Patent number: 11075268
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: July 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
  • Publication number: 20210143254
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 13, 2021
    Inventors: Jiehui SHU, Rinus Tek Po LEE, Baofu ZHU
  • Publication number: 20210118993
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Julien Frougier, Ali Razavieh
  • Patent number: 10985244
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 20, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Shesh Mani Pandey, Chung Foong Tan, Baofu Zhu
  • Publication number: 20210050419
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 18, 2021
    Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
  • Publication number: 20210043766
    Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Baofu Zhu, Shesh Mani Pandey, Jiehui Shu, Sipeng Gu, Haiting Wang
  • Patent number: 10910276
    Abstract: A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yongjun Shi, Xinyuan Dou, Chun Yu Wong, Hongliang Shen, Baofu Zhu
  • Publication number: 20200411638
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Inventors: Shesh Mani PANDEY, Chung Foong TAN, Baofu ZHU
  • Patent number: 10164099
    Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
  • Publication number: 20180233415
    Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.
    Type: Application
    Filed: April 6, 2018
    Publication date: August 16, 2018
    Inventors: Shesh Mani PANDEY, Baofu ZHU, Srikanth Balaji SAMAVEDAM
  • Patent number: 10020386
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage, analog bipolar devices and methods of manufacture. The structure includes: a base region formed in a substrate; a collector region formed in the substrate and comprising a deep n-well region and an n-well region; and an emitter region formed in the substrate and comprising a deep n-well region and an n-well region.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Baofu Zhu
  • Publication number: 20180175198
    Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 21, 2018
    Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
  • Patent number: 10002793
    Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 19, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, David P. Brunco, Jinping Liu, Baofu Zhu, Shesh Mani Pandey
  • Patent number: 9966313
    Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shesh Mani Pandey, Baofu Zhu, Srikanth Balaji Samavedam
  • Publication number: 20180108732
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 19, 2018
    Inventors: Jiehui Shu, Baofu Zhu, Haifeng Sheng, Jinping Liu, Shesh Mani Pandey, Jagar Singh
  • Patent number: 9947788
    Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
  • Publication number: 20180040516
    Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Shesh Mani PANDEY, Baofu ZHU, Srikanth Balaji SAMAVEDAM
  • Publication number: 20170309623
    Abstract: We disclose semiconductor devices, comprising a semiconductor substrate comprising bulk silicon; and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises a lower portion disposed on the semiconductor substrate and having a first width, and an upper portion disposed on the lower portion and having a second width, wherein the second width is greater than the first width, as well as methods, apparatus, and systems for fabricating such semiconductor devices.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 26, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shesh Mani Pandey, Baofu Zhu