Patents by Inventor Baofu Zhu
Baofu Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113108Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a wall within a metal gate cut in a transistor layer of a semiconductor device, where the wall includes a volume of a gas such as air, nitrogen, or another inert gas. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Sukru YEMENICIOGLU, Leonard P. GULER, Hongqian SUN, Shengsi LIU, Tahir GHANI, Baofu ZHU
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Patent number: 11563085Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.Type: GrantFiled: April 29, 2021Date of Patent: January 24, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
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Patent number: 11362178Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.Type: GrantFiled: November 7, 2019Date of Patent: June 14, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Jiehui Shu, Rinus Tek Po Lee, Baofu Zhu
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Patent number: 11362177Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.Type: GrantFiled: January 28, 2020Date of Patent: June 14, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Ali Razavieh, Julien Frougier
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Patent number: 11239315Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.Type: GrantFiled: February 3, 2020Date of Patent: February 1, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Shiv Kumar Mishra, Baofu Zhu, Arkadiusz Malinowski, Kaushikee Mishra
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Patent number: 11239366Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.Type: GrantFiled: January 30, 2020Date of Patent: February 1, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Wenjun Li, Man Gu, Baofu Zhu
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Patent number: 11205699Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.Type: GrantFiled: October 17, 2019Date of Patent: December 21, 2021Assignee: GlobalFoundries U.S. Inc.Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Julien Frougier, Ali Razavieh
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Patent number: 11177385Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.Type: GrantFiled: February 4, 2020Date of Patent: November 16, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Haiting Wang, Sipeng Gu, Jiehui Shu, Baofu Zhu
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Patent number: 11094822Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.Type: GrantFiled: January 24, 2020Date of Patent: August 17, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Arkadiusz Malinowski, Baofu Zhu, Judson R. Holt, Shiv Kumar Mishra
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Publication number: 20210249508Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.Type: ApplicationFiled: April 29, 2021Publication date: August 12, 2021Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
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Publication number: 20210242339Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.Type: ApplicationFiled: January 30, 2020Publication date: August 5, 2021Inventors: Wenjun Li, Man Gu, Baofu Zhu
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Publication number: 20210242306Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.Type: ApplicationFiled: February 3, 2020Publication date: August 5, 2021Inventors: Shiv Kumar MISHRA, Baofu ZHU, Arkadiusz MALINOWSKI, Kaushikee MISHRA
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Publication number: 20210242344Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Inventors: Haiting Wang, Sipeng Gu, Jiehui Shu, Baofu Zhu
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Publication number: 20210233999Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.Type: ApplicationFiled: January 28, 2020Publication date: July 29, 2021Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Ali Razavieh, Julien Frougier
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Publication number: 20210234045Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.Type: ApplicationFiled: January 24, 2020Publication date: July 29, 2021Inventors: Arkadiusz Malinowski, Baofu Zhu, Judson R. Holt, Shiv Kumar Mishra
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Patent number: 11075268Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.Type: GrantFiled: August 15, 2019Date of Patent: July 27, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
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Publication number: 20210143254Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.Type: ApplicationFiled: November 7, 2019Publication date: May 13, 2021Inventors: Jiehui SHU, Rinus Tek Po LEE, Baofu ZHU
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Publication number: 20210118993Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Julien Frougier, Ali Razavieh
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Patent number: 10985244Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.Type: GrantFiled: June 25, 2019Date of Patent: April 20, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Shesh Mani Pandey, Chung Foong Tan, Baofu Zhu
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Publication number: 20210050419Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.Type: ApplicationFiled: August 15, 2019Publication date: February 18, 2021Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu