Abstract: A graphics controller providing for efficient pixel value transformations. A graphics controller interfaces between a host and a graphics display device for displaying pixels having pixel values. The graphics controller includes a solarizing circuit having means for transforming an original pixel value to a transformed pixel value according to a transform function, said transform function having a negative slope at said original pixel value.

Abstract: A method and graphics controller for processing an image is provided wherein color filter array (CFA) data representing the image is received from a digital image capture device into a buffer, a digital filter effect is applied to the CFA data to generate filtered CFA data representing a filtered image, and the filtered image is displayed in real time on a display.

Abstract: A hardware implemented method for resizing an image is provided. In this method, the image is captured and a size of the image is calculated as the image is being received by a display controller. Thereafter, a scaling ratio is calculated based on the calculated size of the image and an output image size. The display controller then scales the image according to the calculated scaling ratio. A display controller and a resizer for resizing the image are also described.

Abstract: Provided is a method and apparatus for generating a single header from a stream of image data. A first frame of image data of the stream of image data is received by a graphics controller, which generates the header. The header is then stored in buffers of a memory of the graphics controller. Subsequently, encoded image data of the first frame of image data and subsequent frames of image data are stored at an offset from the header within the buffers. Thereafter, when a processor decodes the encoded image data, the processor retrieves the contents of the buffer having the header of the first frame of image data and encoded image data.

Abstract: A hardware implemented method for incorporating a border region within an image region is provided. In this hardware implemented method, a position of a pixel along a line within the image region is first computed. The position of the pixel is then compared with an offset value, whereby the offset value defines boundaries of the border region along the line. Thereafter, an image pixel or a color of the border region is selected for display based upon the position of the pixel relative to the offset value. An apparatus and a display controller for incorporating the border region within the image region are also described.

Abstract: A method for concurrently displaying an image and a video on a display having memory integrated therein comprises receiving position data defining a position of a top image region, receiving video data from a video source, and passing the video data directly to the display, i.e., without first storing the image within video RAM. In a first mode video data is passed directly to the display only when it corresponds to pixels outside of the top image region. In a second mode, video data is passed directly to the display such that entire successive images are wholly displayed within the top image region. The top image region is smaller than the entire display region.

Abstract: A graphics controller for flicker filtering interlaced image data is provided. The graphics controller includes a buffer and a memory region. A flicker filter for reducing a flicker of a display presented through an interlaced scan is also provided. The flicker filter is configured to receive interlaced image data prior to any received image data being stored in the memory region. The flicker filter outputs filtered data defining a pixel. The filtered data is stored in the memory region such that two pixels can be output in one memory access to the memory region. Flicker filter enabling circuitry in communication with the buffer is provided. The flicker filter enabling circuitry is configured to supply an even segment and a corresponding odd segment of the interlaced image data to the flicker filter. An apparatus and methods for processing and storing image data having an interlaced format are also provided.

Abstract: A graphics controller and associated method of operation is provided. The graphics controller includes a memory for receiving image data from an image producing source. The graphics controller also includes an image data wrapper module having circuitry that operates independent of a processor external to the graphics controller. The image data wrapper module is configured to read image data from the memory and package the image data with transmission protocol formatting for transmission from the graphics controller to a memory card that is external to the graphics controller. The graphics controller further includes a memory card interface configured to enable transmission of the image data, having been packaged by the image data wrapper module, from the graphics controller to the memory card.

Abstract: A digital imaging device is operated to capture a first image in a digital format. At least two non-contiguous portions of the first image are rendered in a display of the digital imaging device. The at least two non-contiguous portions of the first image are used to align a live version of a second image in the display, wherein the second image is an extension of the first image. The second image is captured in a digital format. A corner matching algorithm is applied to determine an offset of the second image with respect to the first image, wherein the offset is required to achieve a substantially accurate alignment of the first and second images. Application of the corner matching algorithm is limited to an overlap region intervening between the at least two non-contiguous portions of the first image.

Abstract: A graphics controller including a memory and a contrast adjustment module is provided to perform on-board histogram stretching. The memory is configured to store a histogram table for a digital image. The contrast adjustment module is configured to read the histogram table stored in the memory and compute a histogram stretching transfer function based on the read histogram table. The contrast adjustment module is further configured to apply the computed histogram stretching transfer function to digital image data to be subsequently received by the contrast adjustment module.

Abstract: An overlay control circuit and method. In a preferred embodiment of the invention, a graphics controller provides main image data and overlay image data to a display device and includes a memory for storing the main image data and the overlay image data and a logic circuit for producing a signal that, in an active state, indicates that a particular location in the display device is to be represented by the overlay image data. The overlay control circuit fetches the main image data from the memory and is further adapted to respond to a transition in the indicating signal to the active state by halting the fetching.

Abstract: The invention is directed to specifying addresses in a memory for each sample in a minimum coded unit. Preferably, the samples are presented in a predetermined sequence to the memory for storage. For each sample, its presentation to the memory is detected and an offset parameter is provided. Addresses are specified by adding the offset parameter to a base address. When addresses are created for all of the samples that define a particular pixel, all of the addresses are for locations in a particular row of the memory. This allows the samples that define a pixel to be read in one or two read operations.

Abstract: The invention is directed to a method and apparatus for transforming the dimensions of an image represented by block-interleaved data. The method comprises: (a) storing a first minimum coded unit of the image data in a first memory; (b) dimensionally transforming the first minimum coded unit; and (c) storing a second minimum coded unit of the image data in the first memory. Steps (b) and (c) are performed after step (a). In addition, step (b) is performed before: starting to store any third minimum coded unit in the memory after step (c). The apparatus comprises a first memory, a storing circuit, a dimensional transforming circuit, and a timing control circuit. Preferably, the first memory is sized for storing no more than two minimum coded units.

Abstract: The invention is directed to a method and apparatus for storing image data received in a block-interleaved format using an MCU buffer. A first minimum coded unit of the image data is stored in a first memory. The image data in the first minimum coded unit is grouped into pixels. The grouped image data is stored in a second memory as a second minimum coded unit of the image data. Preferably, the image data is converted from a first color format to a second color format. Further, the image is preferably dimensionally transformed.

Abstract: A method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths. Each output path includes a buffer for holding respective portions of the data. A value representative of at least the number of said buffers that are nearly empty of data as compared to a predetermined threshold is determined, and the transmission rate of the input path is adjusted according to said value. Preferably, the buffers are display pipes provided in a graphics controller IC for interfacing between one or more hosts and a graphics display device.

Abstract: The invention is directed to a method and apparatus for serially receiving and dimensionally transforming an image in an ordered sequence of interleaved blocks. Each block comprises an ordered sequence of samples of the image, and the samples of a single block all corresponding to a single color component. The method includes steps of counting the samples in the order received to determine a sequence number for each sample, comparing the sequence number with a set of predetermined values; and dimensionally transforming the image by either discarding the sample or storing the sample in a memory depending on the result of the comparison.

Abstract: A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external device. The chip select module includes an address space configured to store addresses associated with the external device. The address space provides an address section. The address section is associated with the external device and is subdivided into address sub-sections associated with an address range and assigned through the chip select signal. The address sub-sections are configured to determine a bus cycle based on an association with either the CPU monitoring a wait line between the CPU and the external device or the CPU waiting for a number of wait states. A device and a method for optimizing a bus cycle length between a CPU and an external device in communication with the CPU are provided.

Abstract: A hardware implemented method for rotating an image about a user defined reference point is provided. In this method, the user defined reference point is received and the user defined reference point is capable of being defined outside the image. Subsequently, a position of the image is calculated whereby the position defines a location of the image after rotation about the user defined reference point. An order to fetch one or more image pixels from memory is then calculated. The order defines a rotation of the image after rotation about the user defined reference point. Thereafter, the image pixels are fetched from the memory according to the calculated order. An apparatus and a display controller for rotating the image about the user defined reference point also are described.

Abstract: A method for incorporating a border around a displayed image is provided. The method initiates with identifying a main image. The method includes selecting a border image to be associated with the main image. Then, the border image is mapped to a table such that each pixel of the border image is represented by a corresponding single bit in the table. The mapping to the table includes defining a first single bit value for respective border image pixels and defining a second single bit value for respective main image pixels. The method includes applying the table to a display of the main image in order to incorporate the border image with the main image. A graphics processing device and a device configured to generate a border for a displayed image are included.

Abstract: A data pipeline and clock control (relationship) that allows image data from a camera to pass directly through a display controller to an LCD without being written into, temporarily stored, and read out of a display buffer, e.g. a VRAM, is provided. Elimination of the video memory (VRAM) lowers the chip cost, reduces the power requirements, reduces delay due to writing and reading from the video memory, and reduces the pin count since fewer power pins are required.