Abstract: A graphics controller for preparing data to be presented on a display through an interlaced scan is provided. The graphics controller includes a memory and a line buffer adapted to receive video data. Data arrangement circuitry in communication with the line buffer is included. The data arrangement circuitry is configured to process the received video data in order to store the received data in the memory as an even segment and a corresponding odd segment, the even segment associated with data from a line of an even field, the odd segment associated with data from a line of an odd field, the even segment and the corresponding odd segment defining a pixel of data. A single pipe buffer configured to retrieve the even segment and the corresponding odd segment in a single memory access to the memory is included. A system using the graphics controller and a method of storing and retrieving pixel data from memory are also provided.

Abstract: The invention is directed to a method and apparatus for reducing the transmission requirements of a system for transmitting image data to a display device. The image data is stored in a memory. A portion of the image data is selected so that remaining image data is not selected. The selected portion of the image data is fetched from the memory while the remaining image data is not fetched from the memory.

Abstract: The invention is directed to a method and apparatus for reducing the bandwidth required to transmit image data to a display device. It is contemplated that the image data represents a plurality of pixels defining an image for display on the display device, and that the image data is transmitted in a data stream with the data being in a predetermined order of pixel components. The method comprises the steps of receiving the image data from the data stream, and transforming the image data as it is received by selectively storing some of the image data in a memory for access by the display device and discarding other of the image data.

Abstract: A memory controller includes logic for requesting a read operation from memory and logic for generating an address for the read operation. The memory controller also includes logic for storing both, data associated with the address and data associated with a consecutive address in temporary storage. Logic for determining if a request for data associated with a next read operation is for the data associated with the consecutive address in the temporary storage is also provided. A method for optimizing memory bandwidth, a device and an integrated circuit are also provided.

Abstract: A graphics controller for flicker filtering interlaced image data is provided. The graphics controller includes a buffer and a memory region. A flicker filter for reducing a flicker of a display presented through an interlaced scan is also provided. The flicker filter is configured to receive interlaced image data prior to any received image data being stored in the memory region. The flicker filter outputs filtered data defining a pixel. The filtered data is stored in the memory region such that two pixels can be output in one memory access to the memory region. Flicker filter enabling circuitry in communication with the buffer is provided. The flicker filter enabling circuitry is configured to supply an even segment and a corresponding odd segment of the interlaced image data to the flicker filter. An apparatus and methods for processing and storing image data having an interlaced format are also provided.

Abstract: A graphics controller for preparing data to be presented on a display through an interlaced scan is provided. The graphics controller includes a memory and a line buffer adapted to receive video data. Data arrangement circuitry in communication with the line buffer is included. The data arrangement circuitry is configured to process the received video data in order to store the received data in the memory as an even segment and a corresponding odd segment, the even segment associated with data from a line of an even field, the odd segment associated with data from a line of an odd field, the even segment and the corresponding odd segment defining a pixel of data. A single pipe buffer configured to retrieve the even segment and the corresponding odd segment in a single memory access to the memory is included. A system using the graphics controller and a method of storing and retrieving pixel data from memory are also provided.