Abstract: An N-bit control word may be parsed into individual control bits and the individual bits may be inserted into the least significant bit (“LSB”) of N data words. The respective LSBs of the N data words may be mapped into particular bit positions of a control register. When a device receives the N data words, the respective LSBs of the N data may be stored in their designated bit position of the control register. The sender need not specify the address of the control register.

Abstract: One embodiment is directed to a method that includes inspecting a frame of image data transmitted as a stream of pixels. At least one of the pixels in the stream is selected and the color of selected pixels is changed. The steps of inspecting, selecting, and changing the color of selected pixels may be performed as the data is transmitted. The frame may be transmitted for storing in a memory and the steps may be performed as the frame is stored in the memory. Alternatively, the frame may be transmitted from a memory and the steps may be performed as the frame is fetched from in the memory. The selected pixels may be pixels within a particular region of the frame or the selected pixels may have a particular color component value.

Abstract: A method for concurrently displaying an image and a video on a display having memory integrated therein comprises receiving position data defining a position of a top image region, receiving video data from a video source, and passing the video data directly to the display, i.e., without first storing the image within video RAM. In a first mode video data is passed directly to the display only when it corresponds to pixels outside of the top image region. In a second mode, video data is passed directly to the display such that entire successive images are wholly displayed within the top image region. The top image region is smaller than the entire display region.

Abstract: A graphics controller for animating an overlay is described. The graphics controller includes a host interface for communicating with an external processor and a plurality of registers in communication with the host interface. Logic is configured to periodically change coordinates of an overlay image. The logic responds to values stored in the registers to cause display registers containing the coordinates to be updated every x number of frame refreshes, wherein x is a positive integer.

Abstract: A system and method for conserving memory bandwidth while supporting multiple sprites includes a memory device that stores main display data and the multiple sprites for presentation upon a display device. A display controller populates a fetch table with pixel source identifiers that indicate pixel sources from either the main display data or one of the multiple sprites. The pixel source identifiers correspond to display pixels of the display device. The display controller then utilizes the pixel source identifiers to directly locate the appropriate display pixels from the various pixel sources for providing to the display device.

Abstract: The invention is directed to a method and apparatus for serially receiving and dimensionally transforming an image in an ordered sequence of interleaved blocks. Each block comprises an ordered sequence of samples of the image, and the samples of a single block all corresponding to a single color component. The method includes steps of counting the samples in the order received to determine a sequence number for each sample, comparing the sequence number with a set of predetermined values; and dimensionally transforming the image by either discarding the sample or storing the sample in a memory depending on the result of the comparison.

Abstract: A de-noising circuit for filtering image data is provided. The denoising circuit includes a buffer for storing a portion of the image data and detail detection circuitry configured to determine a filter coefficient to be applied to a reference pixel value within the portion of the image data. A blur filter configured to average values within the portion of the image data is included. The blur filter repeats the reference pixel value as specified by the filter coefficient to generate blurred image data. Selection circuitry configured to select between the blurred image data and the unfiltered image data based on a selection signal from the detail detection circuitry is included. A method for filtering image data and a device are also included.

Abstract: An apparatus comprises a first unit to receive a first frame. The first unit replaces each datum of the first frame with a datum having a particular value if the datum of the first frame is within a region of the first frame. A second frame is thereby created. The first unit also writes the second frame.

Abstract: A method for processing an image is described. In the method, image data representing an image into a memory device. The image data is filtered to obtain a plurality of coefficients representing low and high frequency image data. An area of low frequency data corresponding to one of the coefficients is analyzed to identify a degree of edginess of the region. A threshold is obtained, the threshold varying depending on the degree of edginess. If the coefficient is less than the threshold, it is reduced to zero. Wavelet-based image compression can then be performed on the image using the reduced coefficients.

Abstract: A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel data received into the memory through the write FIFO. The memory has a memory controller having write assembly logic for rearranging the pixel data received by the write FIFO for storage in the memory. The write assembly logic is configured to write data representing a first pixel and a second pixel across a plurality of data segments in the memory, where corresponding bit locations for the data representing the first pixel and the data representing the second pixel are contiguous. A graphics controller having the memory and a method for preventing data corruption from being displayed during an underflow are included.

Abstract: A graphics processor is provided. The graphics processor includes a memory storing image data for presentation and a display memory region in communication with the memory, the display memory region supplying image data to a display panel for presentation. The graphics processor includes bandwidth control logic configured to monitor a lag between an output from the display memory region and an input into the display memory region. The bandwidth control logic is further configured to prevent a level of the display memory from decrementing when the lag between the output and the input is capable of causing corruption on the display panel due to a lack of data from the display memory region. A method for avoiding a buffer under run and a device are included.

Abstract: A memory controller that includes a write first in first out (FIFO) region of the memory for receiving pixel data and a read FIFO region of the memory for accessing the pixel data received through the write FIFO is provided. The memory controller is configured to rearrange the pixel data received by the write FIFO for storage in the memory by writing data representing a first pixel and a second pixel across a plurality of registers in the memory, wherein corresponding bit locations for the data representing the first pixel and the data representing the second pixel are stored within a same one of the plurality of registers. The memory controller is configured to grant access to one of multiple requests for access to the memory based on corresponding bit locations associated with the multiple requests. A graphics controller and a method for prioritizing access to a memory are provided.

Abstract: A system for configuring a chip to perform certain operations is provided. The system includes a CPU. The CPU is in communication with a graphics controller. The graphics controller includes a non-volatile memory for storing a look up table (LUT). The graphics controller further includes a register port. The CPU provides a LUT value to the register port. Look up circuitry, which is in communication with the LUT register port, receives the LUT value from the register port and the LUT circuitry retrieves a corresponding LUT sequence from the LUT. The LUT sequence represents an operation to be performed by the LUT circuitry. The system is further provided with a register block, which can be programmed with values based on the operation to be performed.

Abstract: One embodiment is directed to a gamma correction unit. The gamma correction unit includes a first and at least one second lookup table. In addition, the gamma correction unit includes a first and at least one second selecting circuits, and at least one combining circuit. The first lookup table may store a reference function. Each reference function value may be M bits. The first selecting circuit selects a reference function value in the first lookup table that corresponds with a particular input value. The at least one second lookup table may store a difference function. Each difference function value may be no more than N bits, where M is greater than N. The at least one second selecting circuit selects a difference function value in the second lookup table that corresponds with the particular input value. The at least one combining circuit combines the selected reference function value with the selected difference function value to produce an output value that corresponds with the particular input value.

Abstract: Methods and apparatus for creating a digital image in which exposure varies by region of the image are described. The image may be created from first and second images. In one embodiment, a method comprises writing pixels of the first image that are within a first region of a space to pixel locations in a memory that correspond with coordinates of the respective first image pixels. A replacement pixel is generated by combining a pixel of the first image that is within the first region with a spatially corresponding pixel of a second image. The replacement pixel is written to a pixel location in the memory that corresponds with the coordinates of the replacement pixel. Pixels of the first image that are within a second region of the space may be written to pixel locations in the memory that correspond with the coordinates of the respective first image pixels.

Abstract: One embodiment is directed to a display controller that comprises: (a) a selecting circuit and (b) a filtering circuit. The selecting circuit selects pixels of a frame of image data that are within at least one region of the frame designated for filtering. The filtering circuit modifies the selected pixels according to a filtering operation specified for the filtering region in which the selected pixels are located. In addition, in one embodiment, the selecting circuit selects pixels that are within one of at least two filtering regions, and the filtering circuit modifies the selected pixels according to one of at least two distinct filtering operations. Other embodiments are directed to hardware implemented methods for filtering image data.

Abstract: The invention is directed to a method and apparatus for storing image data received in a block-interleaved format using an MCU buffer. A first minimum coded unit of the image data is stored in a first memory. The image data in the first minimum coded unit is grouped into pixels. The grouped image data is stored in a second memory as a second minimum coded unit of the image data. Preferably, the image data is converted from a first color format to a second color format. Further, the image is preferably dimensionally transformed.

Abstract: At least two sites in a frame of pixels are specified. The sites are arranged in a particular spatial distribution and correspond with the pixel locations of a block of pixels. Block parameters are calculated for each pixel block of first and second frames. The block parameters may be calculated using fewer than all of the bits of each pixel. A block-pair similarity determination for each pair of spatially-corresponding pixel blocks of the first and second frames is generated by determining whether there is a difference between the respective block parameters which is greater than a particular block-level threshold. A frame similarity determination is generated by combining the block-pair similarity determinations. A user-interface indication may be provided, or a frame may be stored, as a result of the frame similarity determination.

Abstract: The invention is directed to a method and apparatus for transforming the dimensions of an image represented by block-interleaved data. The method comprises: (a) storing a first minimum coded unit of the image data in a first memory; (b) dimensionally transforming the first minimum coded unit; and (c) storing a second minimum coded unit of the image data in the first memory. Steps (b) and (c) are performed after step (a). In addition, step (b) is performed before: starting to store any third minimum coded unit in the memory after step (c). The apparatus comprises a first memory, a storing circuit, a dimensional transforming circuit, and a timing control circuit. Preferably, the first memory is sized for storing no more than two minimum coded units.

Abstract: A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and microprocessor operates at a second clock speed. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. An asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor processor is also included. The asynchronous bus interface is configured to be independent of the second clock speed of the microprocessor and a difference between the first clock speed and the second clock speed. Flip flop chain redundancy circuitry is included in the bus interface.