Abstract: A graphics controller for high speed transmission for memory read commands. The graphics controller chip includes a logic circuit coupled to a first memory. The logic circuit is adapted to respond to a first issued command from a CPU by determining whether the condition that a first command is a memory read command is true. If the condition is true, the logic circuit causes the graphics controller chip to store the first command in the first memory and to begin carrying out the first command. If the condition is false, the logic circuit causes the graphics controller chip to check whether the graphics controller chip is ready to carry out the first command. If the graphics controller chip is not ready to carry out the first command, the logic circuit causes the graphics controller chip to continue checking and to send a signal to the CPU indicating that the graphics controller chip is ready to receive a second command from the CPU.

Abstract: Data from a video source are downscaled prior to storage in memory. This results in using less memory to store the image, less bandwidth in transmitting the image to the memory and display, and a reduction in power consumption. Downscaling may use methods of interpolation and a combination of dropping pixels and lines from the original image. The device and method require no decompression of data.

Abstract: A system for translating a portrait-oriented software address to a portrait-oriented yet landscape-configured display address. Based on the orientation of a display device, an address translation system either passes the software address “as is” or translates the address to represent a portrait-oriented display address. A refresh address generator operates alternatively in column-forward and column-reverse modes, and additionally operates alternatively in row forward and row reverse modes to selectively rotate the image.

Abstract: Described is a device and method where pixel data in the display memory are stored such that data for a first display area and the corresponding location in a second display are stored within the same word. For example, the first pixel data in the upper half of the display would be stored in the one half of the word, while the first pixel data in the lower half of the display would be stored in the other half of the word. With the pixel data interleaved as described above, in one memory fetch the data can easily be split into upper and lower portions. Once split, the upper and lower data can be applied in parallel paths to frame rate modulation and dithering circuits and streamed to data formatting circuitry and on to the respective upper and lower display areas.

Abstract: A display controller circuit for controlling a display memory having a plurality of memory locations, each memory location having a memory depth. Pixel data having a pixel data depth and a repeat count having a repeat count depth may be stored in each memory location of the display memory. The repeat count represents the number of times the pixel data is to be repeated for display on the external display device. The display controller circuit may be a “fetch inhibiting” display controller or a “memory saving” display controller. A method for controlling memory having a plurality of memory locations, each memory location having a memory depth, the memory depth divided into a data depth for storing data and an excess depth for storing a repeat count.

Abstract: A display controller configured to communicate with a microprocessor is provided. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. A bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor is included. The bus interface is configured to communicate with a set of command signals. The set of command signals defines both whether read operations and write operations are to occur over a bus cycle and whether valid data exists for each bit of the read operation and the write operation. Each command signal in the set of command signals defines enable data for the read operations or write operations. A system including the display controller and methods for adapting the display controller to communicate with a variety of microprocessors are also included.

Abstract: A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and microprocessor operates at a second clock speed. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. An asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor is also included. The asynchronous bus interface is configured to be independent of the second clock speed of the microprocessor and a difference between the first clock speed and the second clock speed. Flip flop chain redundancy circuitry is included in the bus interface.

Abstract: A video display controller incorporates an improved half-frame buffer that can be implemented and operated at lower cost. In one implementation, the half-frame buffer incorporates a distribution circuit that receives three serial digital signals conveying bits representing red, green and blue (RGB) colors in an image. The distribution circuit multiplexes the RGB bits into a signal parallel register so that a complete set of RGB information can be written to or retrieved from memory during a single clock cycle. Preferably, the distribution circuit is implemented by simple signal-switching logic.

Abstract: An indirect interface of the present invention is for use between a processing device and a display device, the indirect interface using fewer pins by following a set of predetermined rules. Address and data signals are multiplexed onto an address/data bus of the indirect interface so that a single set of pins can be used as both address line/pins and data line/pins. In one preferred embodiment, a processor interface means transfers signals between the indirect interface system and the external processing device and a display interface means transfers signals between the indirect interface system and the external display device. In one preferred embodiment, the signals may be transferred between the indirect interface system and the external processing device using a command cycle followed by at least one data cycle.

Abstract: A graphics controller for high speed transmission for memory read commands. The memory controller chip includes a logic circuit coupled to a first memory. The logic circuit is adapted to respond to a first issued command from a CPU by determining whether the condition that a first command is a memory read command is true. If the condition is true, the logic circuit causes the memory controller chip to store the first command in the first memory and to begin carrying out the first command. If the condition is false, the logic circuit causes the memory controller chip to check whether the memory controller chip is ready to carry out the first command. If the memory controller chip is not ready to carry out the first command, the logic circuit causes the memory controller chip to continue checking and to send a signal to the CPU indicating that the memory controller chip is ready to receive a second command from the CPU.

Abstract: A high performance graphics controller. The graphics controller includes a logic circuit adapted to respond to a first issued command from the CPU by checking whether the memory controller chip is ready to carry out the first command and, if not, to continue checking while sending a signal to the CPU indicating that the memory controller chip is ready to receive a second command from the CPU.

Abstract: A graphics controller for high speed transmission for memory write commands. A memory controller chip includes a logic circuit coupled to a first memory and a second memory. The logic circuit is adapted to respond to a first issued command from a CPU by causing the memory controller chip to store the first command in the first memory and to begin processing the first command. If the CPU issues a second command during the time that the memory controller chip is processing the first command, the logic circuit responds by causing the memory controller chip to store the second command in the second memory.

Abstract: A central processing unit (310) in a display system carries pixel-value signals and software-address signals representing the locations of the pixels whose values the pixel-value signals represent. An address-translation circuit (420) converts those software addresses to logical addresses representing the locations of those pixels in a 90°-rotated version of the image that the software address signals represent, and the logical addresses are applied to an image-buffer memory (410) to specify the locations in which to store the pixel values. A refresh-address circuit (620) generates the address signals used in fetching from the image-buffer memory (410) the values that are applied to a display device (360) employed to display the image. The refresh-address generator (620) is operable alternatively in row-forward and row-reverse modes and alternatively in column-forward and column-reverse modes.