Abstract: A keyboard scan engine integrated on a chipset to initiate a keyscan process. The keyboard scan engine detects a key depression. When in a trusted mode, the keyboard scan engine transmits a key code, corresponding to the key depression, through a trusted internal bus interface. When in a non-trusted mode, the keyboard scan engine transmits the key code through an interface to be processed by an onboard keyboard controller.

Abstract: A method for reducing BIOS resume time from a computer system sleeping state, and corresponding components and system for implementing the method. The method first identifies an operating system (OS) type running on a computer system. Based on the operating system type that is identified, a set of BIOS resume tasks specific to that operating system type are dispatched for execution in response to a sleep mode wake event. Generally, the OS-type specific BIOS resume tasks may be stored on various storage means, such as BIOS devices, operating system files, or as a carrier wave. In one embodiment, various generic BIOS resume tasks and corresponding dispatch flag data are stored in one or more tables. In another embodiment, various sets of BIOS resume tasks are stored in separate tables or lists, wherein the sets of BIOS resume tasks may be operating system type and/or computer platform type specific.

Abstract: In one embodiment of the invention, a performance information associated with a processor is read. A processor performance table that corresponds to the performance information is located. The performance table includes a plurality of performance parameters to control performance of the processor. A performance state (PS) structure is updated using one of the processor performance table and a default table.

Abstract: In one embodiment of the invention, a processor state of a processor is determined upon expiration of a system management interrupt (SMI) timer. The processor state is one of an operational state and a low power state. The SMI timer is loaded with a timer value based on the processor state. The timer value is one of a first value and a second value. The processor is transitioned to one of the operational state and the low power state according to the processor state.

Abstract: A system for measuring and managing thermal operations of a processor core on a semiconductor die using a sensor positioned in a hotspot of the processor core. A measured temperature reading is determined based upon a temperature sensed by the sensor. Interrupt signals and a software readable register indicating temperature information provide feedback about the thermal environment to the processor. Based upon the measured temperature reading, the interrupt signals direct the processor to modify operation.

Abstract: Embodiments of the present invention can receive an indication to place a peripheral device in a low power state. The peripheral device can be coupled to a system through a point-to-point, AC coupled bus structure. To enter the low power state, operating power to the peripheral device can be disabled.

Abstract: An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.

Abstract: A processor's performance state may be adjusted based on processor temperature. On transitions to a lower performance state due to the processor getting hotter, the processor's frequency is reduced prior to reducing the processor voltage. Thus, the processor's performance, as seen by the operating system, is reduced immediately. Conversely, on transitions to a higher performance state, due to the processor cooling down, the processor's frequency is not increased until the voltage is changed to a higher level. An interrupt event may be generated anytime the processor's phase locked loop relocks at a new frequency level. Thus, when the interrupt fires, the operating system can read the processor's performance state. As a result, interrupts are not generated that would cause processor performance to lag the interrupt event.

Abstract: In one embodiment of the invention, a system management interrupt (SMI) handler is invoked in response to an SMI. The SMI handler determines a thermal state of a processor. The SMI handler interacts with one of a speed step technology applet and a thermal driver in a thermal management operating system to transition the processor to one of a low power state and a high power state based on the thermal state according to a native performance control status.

Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

Abstract: A method of creating a thermal influence table to describe thermal relationships between components in a system and use of the thermal influence table in a system is described. The thermal influence matrix may be generated dynamically for a system. The matrix may be used by a thermal management policy to enable a hot device to be cooled by power management of another device in the system.

Abstract: A method for entering a particular C state to save power based on bus master activities. The current method is only applied when the current C state has been promoted to C3 and bus master activity has been detected since the last time BM_STS was sampled. The C3 target state is overridden by the C2 state anytime bus master traffic has occurred since the last time BM_STS was read and cleared. The OS reads the status bit on every idle entry where the target is C3. If the BM_STS is set, the idle handler clears it and enters the C2 state. If the BM_STS bit is clear, the idle handler enters C3. The difference being that the handler will enter C2 only for one instance, but will still keep the target C state set to C3.

Abstract: A demand-based method and system of central processing unit power management. The utilization of a central processing unit (CPU) during a sampling time interval is determined by measuring a time quantum within the sampling time interval during which a central processing unit clock signal is active within a processor core of the CPU. The total number of cycles of the central processing unit clock signal that are applied to the processor core and the period of the central processing unit clock signal are used to determine the time quantum. The utilization may then be expressed in terms of a ratio of the time quantum to the total time interval and used to select a processor performance mode. The CPU is then operated in the selected processor performance mode.

Abstract: A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use a single SMI to initialize each processor, may use the location of a single default SMI handler as a wake-up vector to the second processor, and may patch an instruction pointer to a non-aligned address during the handling of the SMI with the second processor to forgo the traditional extra aligned memory allocation. In addition, one may use unified handler code to handle software generated SMIs on both the first and second processors and may use exit SMM directly after handling a hardware SMI to save execution time.

Abstract: A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received, a first processor checks the state of a second processor, which may be done by checking a storage medium storing values representative of the second processor's state. The first processor handles the SMI or waits for the second processor dependent on the state of the second processor. Furthermore, system management memory is allocated where a first system management memory space assigned to a first processor overlaps a second system management memory space assigned to a second processor, leaving first and second non-overlapping region.

Abstract: A keyboard scan engine integrated on a chipset to initiate a keyscan process. The keyboard scan engine to detect. a key depression. When in a trusted mode, transmitting a key code, corresponding to the key depression, through a trusted internal bus interface.

Abstract: A processor's performance state may be adjusted based on processor temperature. On transitions to a lower performance state due to the processor getting hotter, the processor's frequency is reduced prior to reducing the processor voltage. Thus, the processor's performance, as seen by the operating system, is reduced immediately. Conversely, on transitions to a higher performance state, due to the processor cooling down, the processor's frequency is not increased until the voltage is changed to a higher level. An interrupt event may be generated anytime the processor's phase locked loop relocks at a new frequency level. Thus, when the interrupt fires, the operating system can read the processor's performance state. As a result, interrupts are not generated that would cause processor performance to lag the interrupt event.

Abstract: A demand-based method and system of central processing unit power management. The utilization of a central processing unit (CPU) during a sampling time interval is determined by measuring a time quantum within the sampling time interval during which a central processing unit clock signal is active within a processor core of the CPU. The total number of cycles of the central processing unit clock signal that are applied to the processor core and the period of the central processing unit clock signal are used to determine the time quantum. The utilization may then be expressed in terms of a ratio of the time quantum to the total time interval and used to select a processor performance mode. The CPU is then operated in the selected processor performance mode.

Abstract: In a computer system having a processor capable of operating at a plurality of performance states, including a first and a second performance state, wherein while the processor operates in any of the performance states it executes tasks at an expected processing performance, a system and method for dynamically adjusting to transitions between the first and second performance states. A determination is made that a performance state change is needed and a transition is initiated. The system halts task scheduling, measures CPU performance at the new performance state and resumes task scheduling within the constraints of the new performance state. The system also adjusts tasks as a function of CPU performance within the new performance state, wherein adjusting includes notifying each task of the transition between performance states.

Abstract: A processor's performance state may be adjusted based on processor temperature. On transitions to a lower performance state due to the processor getting hotter, the processor's frequency is reduced prior to reducing the processor voltage. Thus, the processor's performance, as seen by the operating system, is reduced immediately. Conversely, on transitions to a higher performance state, due to the processor cooling down, the processor's frequency is not increased until the voltage is changed to a higher level. An interrupt event may be generated anytime the processor's phase locked loop relocks at a new frequency level. Thus, when the interrupt fires, the operating system can read the processor's performance state. As a result, interrupts are not generated that would cause processor performance to lag the interrupt event.