Patents by Inventor Barnes Cooper

Barnes Cooper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Platform power management based on latency guidance
    Patent number: 8631257
    Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Neil Songer, Barnes Cooper, Paul S. Diefenbaugh
  • Idle duration reporting for power management
    Patent number: 8607075
    Abstract: For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Robert E. Gough, Seh W. Kwa, Neil W. Songer, Jaya L. Jeyaseelan, Barnes Cooper
  • Downstream device service latency reporting for power management
    Patent number: 8601296
    Abstract: For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 3, 2013
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
  • Monitoring transaction requests using a policy engine within a storage drive driver to change power capability and latency settings for a storage drive
    Patent number: 8595522
    Abstract: With embodiments of the invention, a more robust solution is provided using a storage driver that may already be used for the platforms operating system. This is efficient because the storage driver typically already monitors storage drive access requests, and thus knows when traffic is outstanding (performance may be critical) or when it's not outstanding (and power may be saved).
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 26, 2013
    Assignee: Intel Corporation
    Inventors: Barnes Cooper, Faraz A. Siddiqi
  • FAST PLATFORM HIBERNATION AND RESUMPTION OF COMPUTING SYSTEMS
    Publication number: 20130290760
    Abstract: Fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a volatile system memory, a nonvolatile memory, and a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state upon receipt of a request, the transition to the first reduced power state including the processor to store context information for the computer in the volatile system memory.
    Type: Application
    Filed: October 1, 2011
    Publication date: October 31, 2013
    Inventors: Barnes Cooper, Faraz A. Siddiqi
  • Method and apparatus of power management of processor
    Patent number: 8458498
    Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Barnes Cooper, Guy Therien, Eliezer Weissmann, Anil Aggarwal
  • POWER MANAGEMENT OF LOW POWER LINK STATES
    Publication number: 20130132755
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 23, 2013
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough
  • Power management of electronic devices using transitions between link states based on device activity
    Patent number: 8341445
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: December 25, 2012
    Assignee: Intel Corporation
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough
  • Latency based platform coordination
    Patent number: 8332675
    Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 11, 2012
    Assignee: Intel Corporation
    Inventors: Seh W. Kwa, Robert Gough, Neil Songer, Jaya L. Jeyaseelan, Barnes Cooper, Nilesh V. Shah
  • Method and system to enable fast platform restart
    Patent number: 8296553
    Abstract: A method and system to perform a fast reset or restart of a platform by minimizing the hardware initialization of IO devices in the platform during a restart of the platform. The basic input/output system (BIOS) of the platform traps any software initiated reset request (SIRR) or warm reset. The BIOS restores the input/output (IO) devices coupled with the platform to their previous hardware state to avoid the full platform initialization when the SIRR is trapped. The restart of the platform can be performed in a fast manner as the full platform initialization is minimized.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: October 23, 2012
    Assignee: Intel Corporation
    Inventors: Barnes Cooper, Faraz A. Siddiqi, Michael R. Rothman, Vincent J. Zimmer
  • PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE
    Publication number: 20120198248
    Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
    Type: Application
    Filed: April 12, 2012
    Publication date: August 2, 2012
    Inventors: Jaya L. Jeyaseelan, Neil Songer, Barnes Cooper, Paul S. Diefenbaugh
  • Platform power management based on latency guidance
    Patent number: 8176341
    Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Neil Songer, Barnes Cooper, Paul S. Diefenbaugh
  • SYSTEM AND METHOD FOR CONTROLLING PROCESSOR LOW POWER STATES
    Publication number: 20120102349
    Abstract: A next idle state for a processor in a system may be determined based on a previous idle period and a previous idle state. The next idle state for the processor may also be determined based on times when interrupts are generated by devices in the system.
    Type: Application
    Filed: April 19, 2011
    Publication date: April 26, 2012
    Inventors: Susumu Arai, Michael Walz, Barnes Cooper
  • STORAGE DRIVE MANAGEMENT
    Publication number: 20120084582
    Abstract: With embodiments of the invention, a more robust solution is provided using a storage driver that may already be used for the platforms operating system. This is efficient because the storage driver typically already monitors storage drive access requests, and thus knows when traffic is outstanding (performance may be critical) or when it's not outstanding (and power may be saved).
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Barnes Cooper, Faraz A. Siddiqi
  • LATENCY BASED PLATFORM COORDINATION
    Publication number: 20110302626
    Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
    Type: Application
    Filed: August 19, 2011
    Publication date: December 8, 2011
    Inventors: Seh W. Kwa, Robert Gough, Neil Songer, Jaya L. Jeyaseelan, Barnes Cooper, Nilesh V. Shah
  • POWER MANAGEMENT OF LOW POWER LINK STATES
    Publication number: 20110276816
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 10, 2011
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough
  • Power management of low power link states
    Patent number: 7984314
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough
  • System and method for fast platform hibernate and resume
    Patent number: 7971081
    Abstract: In some embodiments, an apparatus includes processor cores, a smaller non-volatile memory, a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores. The apparatus also includes volatile memory to act as system memory for the processor cores, and power management logic to control at least some aspects of power management. In response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory. Other embodiments are described.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventors: Barnes Cooper, Faraz A. Siddiqi
  • System and method for controlling processor low power states
    Patent number: 7930564
    Abstract: A next idle state for a processor in a system may be determined based on a previous idle period and a previous idle state. The next idle state for the processor may also be determined based on times when interrupts are generated by devices in the system.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: April 19, 2011
    Assignee: Intel Corporation
    Inventors: Susumu Arai, Michael Walz, Barnes Cooper
  • LATENCY BASED PLATFORM COORDINATION
    Publication number: 20110078473
    Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
    Type: Application
    Filed: December 3, 2010
    Publication date: March 31, 2011
    Inventors: Seh W. Kwa, Robert Gough, Neil Songer, Jaya L. Jevaseelan, Barnes Cooper, Nilesh V. Shah