Patents by Inventor Barry E. Burke

Barry E. Burke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8536625
    Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Massachusetts Institute of Technology
    Inventor: Barry E. Burke
  • Patent number: 8044119
    Abstract: An insulating material and the method of applying the insulating material to products and systems. The material, method and system may be applied to tubulars used in deep water projects. The insulating material is composed of ceramic particles, epoxy and an acrylate monomer that is a precurser to an acrylic resin, and additives. Equal volumes of a epoxy component mixtures and a curing agent component mixture when heated and mixed together create a liquid insulating material that can be applied to the outer surface of pipe involving a repetitive series of steps controlled by an operator at a main control panel. Pipe unrolled from a pipe reel is straightened and heated. In a heated retort, liquid insulating material is applied to the surface of pipe and cured to the final insulation coating. The final coated pipe can be replaced on the reel for shipment to the job site.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: October 25, 2011
    Inventors: James E. Landry, Barry E. Burke
  • Publication number: 20110062499
    Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 17, 2011
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventor: Barry E. Burke
  • Patent number: 7217601
    Abstract: In accordance with the invention, an electrically conducting charge transfer channel is formed in a semiconductor substrate and an electrically insulating layer is formed on a surface of the substrate; a layer of gate electrode material is formed on the insulating layer. On the gate material layer is formed a first patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gate electrodes, and the first-pattern-exposed regions of the gate material layer are electrically doped. In addition, on the gate material layer is formed a second patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gaps between gate electrodes, and the second-pattern-exposed regions of the gate material layer are etched.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: May 15, 2007
    Assignee: Massachusetts Institute of Technology
    Inventors: Barry E. Burke, Vyshnavi Suntharalingam
  • Patent number: 7173294
    Abstract: The CCD image sensor addresses the problem of noise, due to background charge generated by Compton scattering of gamma rays. In applications, in which an imager must operate in a high-radiation environment, such background noise reduces the video signal/noise. This imager reduces the amount of charge collected from Compton events, while giving up very little sensitivity to photons in the visible/near IR.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 6, 2007
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Barry E. Burke, Robert K. Reich
  • Patent number: 7091530
    Abstract: A charge-coupled device imager including an array of super pixels disposed in a semiconductor substrate having a surface that is accessible to incident illumination. For each super pixel there is provided a plurality of subpixels which each correspond to one in the sequence of image frames. Each subpixel includes a doped photogenerated charge collection channel region opposite the illumination-accessible substrate surface, a charge collection channel region control electrode, doped charge drain regions adjacent to the channel region, a charge drain region control electrode, and a doped charge collection control region. To each subpixel are provided channel region and drain region control voltage connections, for independent collection and storage of photogenerated charge from the substrate at the charge collection channel region of a selected subpixel during one in the sequence of image frames and for drainage of photogenerated charge from the substrate to a drain region.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: August 15, 2006
    Assignee: Massachusetts Institute of Technology
    Inventors: Robert K. Reich, Bernard B. Kosicki, Jonathan C. Twichell, Barry E. Burke, Dennis D. Rathman
  • Patent number: 7074639
    Abstract: Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: July 11, 2006
    Assignee: Massachusetts Institute of Technology
    Inventors: Barry E. Burke, Eugene D. Savoye
  • Patent number: 6917041
    Abstract: An event-driven X-ray CCD imager device uses a floating-gate amplifier or other non-destructive readout device to non-destructively sense a charge level in a charge packet associated with a pixel. The output of the floating-gate amplifier is used to identify each pixel that has a charge level above a predetermined threshold. If the charge level is above a predetermined threshold the charge in the triggering charge packet and in the charge packets from neighboring pixels need to be measured accurately. A charge delay register is included in the event-driven X-ray CCD imager device to enable recovery of the charge packets from neighboring pixels for accurate measurement. When a charge packet reaches the end of the charge delay register, control logic either dumps the charge packet, or steers the charge packet to a charge FIFO to preserve it if the charge packet is determined to be a packet that needs accurate measurement.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: July 12, 2005
    Assignee: Massachusetts Institute of Technology
    Inventors: John P. Doty, George R. Ricker, Jr., Barry E. Burke, Gregory Y. Prigozhin
  • Publication number: 20040026623
    Abstract: An event-driven X-ray CCD imager device uses a floating-gate amplifier or other non-destructive readout device to non-destructively sense a charge level in a charge packet associated with a pixel. The output of the floating-gate amplifier is used to identify each pixel that has a charge level above a predetermined threshold. If the charge level is above a predetermined threshold the charge in the triggering charge packet and in the charge packets from neighboring pixels need to be measured accurately. A charge delay register is included in the event-driven X-ray CCD imager device to enable recovery of the charge packets from neighboring pixels for accurate measurement. When a charge packet reaches the end of the charge delay register, control logic either dumps the charge packet, or steers the charge packet to a charge FIFO to preserve it if the charge packet is determined to be a packet that needs accurate measurement.
    Type: Application
    Filed: March 18, 2003
    Publication date: February 12, 2004
    Inventors: John P. Doty, George R. Ricker, Barry E. Burke, Gregory Y. Prigozhin
  • Publication number: 20020048837
    Abstract: Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.
    Type: Application
    Filed: December 17, 2001
    Publication date: April 25, 2002
    Inventors: Barry E. Burke, Eugene D. Savoye
  • Publication number: 20020017016
    Abstract: An insulating material and the method of applying the insulating material to products and systems. The material, method and system may be applied to tubulars used in deep water projects. The insulating material is composed of ceramic particles, epoxy and an acrylate monomer that is a precurser to an acrylic resin, and additives. Equal volumes of a epoxy component mixtures and a curing agent component mixture when heated and mixed together create a liquid insulating material that can be applied to the outer surface of pipe involving a repetitive series of steps controlled by an operator at a main control panel. Pipe unrolled from a pipe reel is straightened and heated. In a heated retort, liquid insulating material is applied to the surface of pipe and cured to the final insulation coating. The final coated pipe can be replaced on the reel for shipment to the job site.
    Type: Application
    Filed: October 7, 1999
    Publication date: February 14, 2002
    Inventors: JAMES E. LANDRY, BARRY E. BURKE
  • Patent number: 6331873
    Abstract: Provided is a blooming control structure for an imager and a corresponding fabrication method. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: December 18, 2001
    Assignee: Massachusetts Institute of Technology
    Inventors: Barry E. Burke, Eugene D. Savoye
  • Patent number: 5904495
    Abstract: A hybrid integrated circuit and method of fabricating a hybrid integrated circuit. A first wafer is provided having a first surface with a first electrical contact for a first active circuit associated therewith and a second surface. A second wafer is provided having a third surface with a second electrical contact for a second active circuit associated therewith and a fourth surface, the second wafer being chemically thinned at the fourth surface. The first and second wafers are bonded together at an interface between the first and third surfaces such that the first and second electrical contacts are relatively aligned with one another. The fourth surface of the second wafer is processed to define an access via to both the first and second contacts. An electrical interconnection is formed between the first and second contacts within the access via so that the first and second active circuits are electrically interconnected.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: May 18, 1999
    Assignee: Massachusetts Institute of Technology
    Inventors: Barry E. Burke, Bernard B. Kosicki
  • Patent number: 5880777
    Abstract: An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port, a charge-coupled imaging device, an analog signal processor, and an analog-to-digital processor (A/D). The A/D digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: March 9, 1999
    Assignee: Massachusetts Institute of Technology
    Inventors: Eugene D. Savoye, Allen M. Waxman, Robert K. Reich, Barry E. Burke, James A. Gregory, William H. McGonagle, Andrew H. Loomis, Bernard B. Kosicki, Robert W. Mountain, Alan N. Gove, David A. Fay, James E. Carrick
  • Patent number: 5846708
    Abstract: A method and apparatus are disclosed for identifying molecular structures within a sample substance using a monolithic array of test sites formed on a substrate upon which the sample substance is applied. Each test site includes probes formed therein to bond with a predetermined target molecular structure or structures. A signal is applied to the test sites and certain electrical, mechanical and/or optical properties of the test sites are detected to determine which probes have bonded to an associated target molecular structure.
    Type: Grant
    Filed: April 23, 1992
    Date of Patent: December 8, 1998
    Assignee: Massachusetts Institiute of Technology
    Inventors: Mark A. Hollis, Daniel J. Ehrlich, R. Allen Murphy, Bernard B. Kosicki, Dennis D. Rathman, Richard H. Mathews, Barry E. Burke, Mitch D. Eggers, Michael E. Hogan, Rajender Singh Varma
  • Patent number: 5793070
    Abstract: A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: August 11, 1998
    Assignee: Massachusetts Institute of Technology
    Inventor: Barry E. Burke
  • Patent number: 5760431
    Abstract: A multidirectional charge transfer device configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates, each of which is arranged in a first portion of each charge storage region, a plurality of second gates, each of which is arranged in a second portion of each charge storage region, a plurality of third gates, each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates, each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: June 2, 1998
    Assignee: Massachusetts Institute of Technology
    Inventors: Eugene D. Savoye, Barry E. Burke, John Tonry
  • Patent number: 5653939
    Abstract: A method and apparatus are disclosed for identifying molecular structures within a sample substance using a monolithic array of test sites formed on a substrate upon which the sample substance is applied. Each test site includes probes formed therein to bond with a predetermined target molecular structure or structures. A signal is applied to the test sites and certain electrical, mechanical and/or optical properties of the test sites are detected to determine which probes have bonded to an associated target molecular structure.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: August 5, 1997
    Assignees: Massachusetts Institute of Technology, Houston Advanced Research Center, Baylor College of Medicine
    Inventors: Mark A. Hollis, Daniel J. Ehrlich, R. Allen Murphy, Bernard B. Kosicki, Dennis D. Rathman, Chang-Lee Chen, Richard H. Mathews, Barry E. Burke, Mitch D. Eggers, Michael E. Hogan, Rajender Singh Varma
  • Patent number: 5198881
    Abstract: A surface electron barrier region is formed on a semiconductor membrane device by a single step laser process which produces a sharp doping profile in a surface region above the light penetration depth. Enhanced quantum efficiency is observed, and by selectively forming barrier layers of differing depth, a CCD device architecture for two-color sensitivity is achieved. The barrier layer results in enhanced membrane-type and radiation hardened bipolar and CMOS devices.
    Type: Grant
    Filed: August 7, 1991
    Date of Patent: March 30, 1993
    Assignee: Massachusetts Institute of Technology
    Inventors: Jammy C. Huang, Mordechai Rothschild, Barry E. Burke, Daniel J. Ehrlich, Bernard B. Kosicki
  • Patent number: 5105248
    Abstract: An electro-optical device comprising a CCD structure having charge wells, the charges therein being controlled by a modulating signal applied to said CCD structure. A multiple quantum well structure having quantum well regions associated with the charge wells of said CCD structure, the charges in the CCD charge wells determining the value of the electric fields at said quantum well regions and, hence, the electro-absorption effects at said quantum well regions. The intensity of an input electromagnetic wave signal directed through said electro-optical device is thereby spatially modulated by the electro-absorption effects at the quantum well regions of the multiple quantum well structure. A novel CCD structure using quantum well regions to form the charge wells thereof can be used as the CCD structure for controlling the electric fields at the multiple quantum well structure.
    Type: Grant
    Filed: January 11, 1990
    Date of Patent: April 14, 1992
    Assignee: Massachusetts Institute of Technology
    Inventors: Barry E. Burke, William D. Goodhue, Jr., Kirby B. Nichols