Abstract: Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of a conductor. The line is laterally spaced in a direction at a minimum distance from the first row of contacts. The test structure further includes a second row of contacts laterally spaced in the direction from the first row of contacts by a distance equal to two times a minimum pitch. The line is laterally positioned between the first row of contacts and the second row of contacts.

Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.

Abstract: Methods and systems for reducing dark current in a photodiode include heating a photodiode and applying an increasing reverse bias voltage to the heated photodiode to reduce a dark current generated by the photodiode.

Abstract: A three plate MIM capacitor structure includes a three plate MIM capacitor, a first wire in a metal layer above/below the three plate MIM, a second wire below/above the three plate MIM, a third wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first wire and the second and third wires or detecting leakage current across the second wire and the third wire.

Abstract: A three plate MIM capacitor test structure includes a three plate MIM capacitor, a first test wire in a metal layer above/below the three plate MIM, a second test wire below/above the three plate MIM, a third test wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first test wire and the second and third test wires or detecting leakage current across the second test wire and the third test wire.

Abstract: Methods and systems for reducing dark current in a photodiode include heating a photodiode above room temperature. A reverse bias voltage is applied to the heated photodiode to reduce a dark current generated by the photodiode.

Abstract: A method of measuring semiconductor output characteristics is provided that includes connecting a pulse generator to the gate structure of a semiconductor device, and applying a plurality of voltage pulses at least some of which having a different pulse width to the gate structure of the semiconductor device. The average current is measured from the drain structure of the device for a duration of each pulse of the plurality of pulses. From the measured values for the average current, a self-heating curve of the average current divided by the pulse width is plotted as a function of the pulse width. The self-heating curve is then extrapolated to a pulse width substantially equal to zero to provide a value of drain current measurements without self-heating effects.

Abstract: A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pFET) area of the CMOS device and an n-channel FET (nFET) area of the CMOS device, depositing a high-k dielectric on the interfacial layer in both the pFET area and the nFET area, selectively forming a first metal layer on the high-k dielectric in only the pFET area, and depositing a second metal layer on the first metal layer in the pFET area and on the high-k dielectric in the nFET area. The method also includes performing an anneal that increases a thickness of the interfacial layer in only the pFET area.

Abstract: A method for gaining access beyond a restricted access gateway includes an access key sequence stored on memory of a device. The access key sequence includes a sequence of key entries and key touch movements. An entered request sequence including keys activated by touch on a keyboard of the device and directions of touch movements made on the keyboard is recorded. With an access controller, it is determined whether the recorded entered request sequence matches the access key sequence. Access beyond the restricted access gateway is granted to functions when the recorded entered request sequence matches the access key sequence.

Abstract: Systems for reducing dark current in a photodiode include a heater configured to heat a photodiode above room temperature. A reverse bias voltage source is configured to apply a reverse bias voltage to the heated photodiode to reduce a dark current generated by the photodiode. A control system is configured to trigger the reverse bias voltage source to increase the reverse bias voltage.

Abstract: A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.

Abstract: A method for gaining access beyond a restricted access gateway includes an access key sequence stored on memory of a device. The access key sequence includes a sequence of key entries and key touch movements. An entered request sequence including keys activated by touch on a keyboard of the device and directions of touch movements made on the keyboard is recorded. With an access controller, it is determined whether the recorded entered request sequence matches the access key sequence. Access beyond the restricted access gateway is granted to functions when the recorded entered request sequence matches the access key sequence.

Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.

Abstract: Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage Vhigh; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.

Abstract: Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.

Abstract: Systems for reducing dark current in a photodiode include a heater configured to heat a photodiode above room temperature. A reverse bias voltage source is configured to apply a reverse bias voltage to the heated photodiode to reduce a dark current generated by the photodiode.

Abstract: Methods and systems for reducing dark current in a photodiode include heating a photodiode above room temperature. A reverse bias voltage is applied to the heated photodiode to reduce a dark current generated by the photodiode.

Abstract: Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.

Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.