Abstract: A seismic data acquisition unit includes a housing, and disposed within the housing, communication circuitry, and circuitry configured to detect and digitize seismic signals. The communication circuitry includes a first transmitter plate, a second transmitter plate, a first receiver plate, a second receiver plate, and a driver. The first and second transmitter plates, and first and second receiver plates, are adjacent a wall of the housing. The driver is coupled to the first transmitter plate and the second transmitter plate. The receiver is coupled to the first receiver plate and the second receiver plate. The communication circuitry transmits digitized seismic signals via a first capacitor that includes the first transmitter plate, and a second capacitor that includes the second transmitter plate. The communication circuitry receives information via a third capacitor that includes the first receiver plate, and a fourth capacitor that includes the second receiver plate.

Abstract: A seismic data acquisition unit includes a housing, and disposed within the housing, communication circuitry, and circuitry configured to detect and digitize seismic signals. The communication circuitry includes a first transmitter plate, a second transmitter plate, a first receiver plate, a second receiver plate, and a driver. The first and second transmitter plates, and first and second receiver plates, are adjacent a wall of the housing. The driver is coupled to the first transmitter plate and the second transmitter plate. The receiver is coupled to the first receiver plate and the second receiver plate. The communication circuitry transmits digitized seismic signals via a first capacitor that includes the first transmitter plate, and a second capacitor that includes the second transmitter plate. The communication circuitry receives information via a third capacitor that includes the first receiver plate, and a fourth capacitor that includes the second receiver plate.

Abstract: A seismic data acquisition unit includes circuitry to detect and digitize a seismic signal, and timing circuitry to control a time of acquisition of each sample of the seismic signal. The timing circuitry include a voltage controlled oscillator (VCO), a local clock incremented by the VCO, and a reference time receiver. The timing circuitry powers on the reference time receiver to generate a reference time value based on signals received from a reference time source, and measures time deviation of the local clock from the reference time value. The timing circuitry determines an adjustment value to apply to the VCO over a time interval during which the reference time receiver is not powered on. The adjustment value is selected to gradually bring the local clock into synchronization with the reference time source over the time interval at a time that the reference time receiver is to be next powered on.

Abstract: A seismic data acquisition unit includes circuitry to detect and digitize a seismic signal, and timing circuitry to control a time of acquisition of each sample of the seismic signal. The timing circuitry include a voltage controlled oscillator (VCO), a local clock incremented by the VCO, and a reference time receiver. The timing circuitry powers on the reference time receiver to generate a reference time value based on signals received from a reference time source, and measures time deviation of the local clock from the reference time value. The timing circuitry determines an adjustment value to apply to the VCO over a time interval during which the reference time receiver is not powered on. The adjustment value is selected to gradually bring the local clock into synchronization with the reference time source over the time interval at a time that the reference time receiver is to be next powered on.

Abstract: A system for seismic data acquisition includes data recorders that lack external electrical connectors. A seismic data recorder includes a housing. Within the housing the seismic data recorder includes circuitry configured to detect and digitize seismic signals and communication circuitry. The communication circuitry includes a first transmitter plate adjacent a wall of the housing, and a first driver coupled to the first transmitter plate. The communication circuitry configured to communicate the digitized seismic signals to a data retrieval unit that is external to the data acquisition unit via a capacitor formed by the first transmitter plate, the wall of the housing, and a receiver plate external to the housing.

Abstract: A system for seismic data acquisition includes data recorders that lack external electrical connectors. A seismic data recorder includes a housing. Within the housing the seismic data recorder includes circuitry configured to detect and digitize seismic signals and communication circuitry. The communication circuitry includes a first transmitter plate adjacent a wall of the housing, and a first driver coupled to the first transmitter plate. The communication circuitry configured to communicate the digitized seismic signals to a data retrieval unit that is external to the data acquisition unit via a capacitor formed by the first transmitter plate, the wall of the housing, and a receiver plate external to the housing.

Abstract: Embodiments provide apparatuses and systems in which slave power sequencers share a command bus and power sequence respective power groups through power sequence states of a power sequencing protocol in response to commands on the command bus. In some examples, a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command. Other examples are described and claimed.

Abstract: Sharing firmware among a plurality of agents including a plurality of central processing units (CPUs) on a node is described. In an example, a computing node includes: a bus; a non-volatile memory, coupled to the bus, to store firmware for the plurality of agents; a power sequencer to implement a power-up sequence for the plurality of CPUs; a plurality of power control state machines respectively controlling states of the plurality of CPUs based on output of the power sequencer; and a bus controller to selectively couple the plurality of agents to the non-volatile memory based on state of the plurality of power control state machines.

Abstract: Embodiments provide apparatuses and systems in which slave power sequencers share a command bus and power sequence respective power groups through power sequence states of a power sequencing protocol in response to commands on the command bus. In some examples, a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command. Other examples are described and claimed.

Abstract: A blade server system and method for virtually hot plugging and virtually hot removing functions in a shared I/O environment. A management node physically hot inserts and hot removes an I/O node in the server system without a compute node being aware of the hot insert and hot removal. The management node and the compute node create and remove virtual links between the compute node and the virtual functions.

Abstract: A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Abstract: A method includes providing a bridge device (105) connected to a host computing device (101-1, 101-2) and a peripheral device (103-1, 103-2, 103-N, 403-1, 403-2, 405-1, 405-2, 405-3), the bridge device (105) being configured to communicatively couple the host device (101-1, 101-2) to the peripheral device (103-1, 103-2, 103-N, 403-1, 403-2, 405-1, 405-2, 405-3); and preventing execution of a hardware enumeration process (313) in the host device (101-1, 101-2) until completion of a resource allocation process (303) in the bridge device (105).

Abstract: A system for transforming a single root input/output virtualization (SR-IOV) function to appear as a legacy function, and a corresponding method includes a switch platform coupled between a legacy host and a SR-IOV-enabled device. The switch platform includes a processor programmed to discern configuration cycles by type and to process the configuration cycles, and one or more local registers that store data related to the configuration cycles.

Abstract: A system for transforming a single root input/output virtualization (SR-IOV) function to appear as a legacy function, and a corresponding method includes a switch platform coupled between a legacy host and a SR-IOV-enabled device. The switch platform includes a processor programmed to discern configuration cycles by type and to process the configuration cycles, and one or more local registers that store data related to the configuration cycles.

Abstract: A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Abstract: A method includes providing a bridge device (105) connected to a host computing device (101-1, 101-2) and a peripheral device (103-1, 103-2, 103-N, 403-1, 403-2, 405-1, 405-2, 405-3), the bridge device (105) being configured to communicatively couple the host device (101-1, 101-2) to the peripheral device (103-1, 103-2, 103-N, 403-1, 403-2, 405-1, 405-2, 405-3); and preventing execution of a hardware enumeration process (313) in the host device (101-1, 101-2) until completion of a resource allocation process (303) in the bridge device (105).

Abstract: There is provided a system and method of controlling transaction flow in a communications interface. An exemplary system comprises a first buffer configured to hold packets of a first packet type, and a second buffer configured to hold packets of a second packet type. An exemplary system also comprises a counter configured to track a delay-reference of packets held in the second buffer. An exemplary system also comprises a controller configured to receive packets from a host and send packets of the first packet type to the first buffer and to send packets of the second packet type to the second buffer, the controller being further configured to stop receiving packets if the delay-reference meets or exceeds a specified threshold.

Abstract: A server is capable of maintaining a power budget. The server comprises a central processing unit (CPU), a management processor, a power measurement circuit, and a comparison circuit. The comparison circuit receives real time power measurements from the power measurement circuit. A register includes a power budget value from the management processor. The management processor selects a system power performance state for the CPU that utilizes a level of power approximately equal to the power budget value.

Abstract: A method determines actual power consumption for system power performance states (SPP-states) of a server. The method comprises initializing the server, performing a worst case workload test, measuring power consumption of the server at one or more SPP-states, and adjusting values in a lookup table to reflect the measured power consumption of the server.

Abstract: A system and method for connecting electrical components. More specifically, a method includes positioning a first set of electrical contacts of a first device opposite from a second set of electrical contacts of a second device, and activating a mechanism configured to rotate the first set of electrical contacts between an engaged position against the second set of electrical contacts and a disengaged position offset from the second set of electrical contacts.