Abstract: A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

Abstract: A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

Abstract: A method determines actual power consumption for system power performance states (SPP-states) of a server. The method comprises initializing the server, performing a worst case workload test, measuring power consumption of the server at one or more SPP-states, and adjusting values in a lookup table to reflect the measured power consumption of the server.

Abstract: A server is capable of maintaining a power budget. The server comprises a central processing unit (CPU), a management processor, a power measurement circuit, and a comparison circuit. The comparison circuit receives real time power measurements from the power measurement circuit. A register includes a power budget value from the management processor. The management processor selects a system power performance state for the CPU that utilizes a level of power approximately equal to the power budget value.

Abstract: In electronic systems, signaling problems frequently occur when a device is driving a signal on a line to an incorrect level at a particular point in time. When production schedules do not permit fixing the defects in the errant device, programmable logic has been employed to work around the problems caused by the defective device. Higher device speeds and increasingly complex bus protocols have made the technique of singly using programmable logic, more difficult to implement. The addition of bidirectional switches integrated with and controlled by programmable logic in a monolithic integrated circuit allows the programmable logic device to respond more quickly while at the same time consuming less printed circuit board space. Additionally, the invention provides for termination of the isolated device and/or signal line stubs.

Abstract: A method for powering up a removable circuit card when it is inserted into a card slot of a computer system includes providing power and a clock signal to the circuit card. A communication link is electrically coupled to the circuit card after both the power and the clock signal are provided to the circuit card.

Abstract: A computer system has a bus, a connector for a circuit card, and a clamp configured to selectively prevent removal of the circuit card from the connector when the clamp is engaged. The computer system has circuitry connected to monitor the engagement status of the clamp and to regulate delivery of power to the connector based on the engagement state of the clamp.

Abstract: A computer system has a skew compensation circuit for synchronizing the phase of a first periodic signal in one device with a second periodic signal in a second device connected to the first device by a connection that imposes a propagation delay. The skew compensation circuit has a receiver connected to receive the second periodic signal delayed by the propagation delay and circuitry for providing a delay signal representative of the propagation delay. The skew compensation circuit further includes a generator connected to generate the first periodic signal in phase with the second periodic signal based on the first periodic signal and the delay signal.

Abstract: A computer system has a central processing unit and a bus. A first bus device and a second bus device are connected to the bus. A circuit is connected to configure the second bus device to be addressable by the central processing unit via the bus only by interaction with the first bus device. The first bus device may be an I.sub.2 O processor, and the second bus device may be an I.sub.2 O subordinate bus device.

Abstract: A computer system determines the presence of a device attached to a system bus that responds to I/O or memory reads by driving the data lines of that bus to values normally present on an undriven bus. The data bus is first driven to a value other than its undriven value, such as to 00h. Then, circuitry measures the time it takes on an I/O or memory read for the data bus to return to its normally undriven value. If the response time is less than the time it takes for an undriven data bus to return to its undriven state, then an expansion board is driving the data bus to its normally undriven value. This indicates that the expansion board is responding to an I/O or memory read on the data bus, even though it is responding by driving that bus to its normally undriven value. Further, by determining the maximum response time of a device, system performance is then improved by tuning cycle time to correspond to that maximum response time.

Abstract: A protection circuit for a computer system having PCI expansion cards and PCI expansion slots with multiple power rails for supplying power to the PCI expansion cards, the protection circuit including a current monitor that monitors the current levels drawn by the PCI expansion card at each power rail; an inrush current controller for controlling the initial current applied to each of the power rails when an expansion card is initially inserted into an expansion slot; a voltage monitor that monitors the voltage levels applied to selected power rails; and a disconnector for disconnecting the power to the PCI expansion slot when either the current level drawn by the PCI expansion card at any of the power rails goes beyond a selected range or when the voltage levels at any of the selected monitored power rails are below a selected threshold or when commanded by the computer system.

Abstract: A computer system determines the presence of a device attached to a system bus that responds to I/O or memory reads by driving the data lines of that bus to values normally present on an undriven bus. The data bus is first driven to a value other than its undriven value, such as to 00h. Then, circuitry measures the time it takes on an I/O or memory read for the data bus to return to its normally undriven value. If the response time is less than the time it takes for an undriven data bus to return to its undriven state, then an expansion board is driving the data bus to its normally undriven value. This indicates that the expansion board is responding to an I/O or memory read on the data bus, even though it is responding by driving that bus to its normally undriven value. Further, by determining the maximum response time of a device, system performance is then improved by tuning cycle time to correspond to that maximum response time.

Abstract: In a system that executes the method according to the invention, each slot on the system bus is individually enabled at start-up and each address of an address range is read to determine whether an expansion board is installed in the slot and is responding to a read from that I/O address. If the data value returned by the I/O read is not equal to the undriven value of the data bus, then it is known that the expansion board is responding to that I/O address. Otherwise, a second read of the I/O address is performed, and the values of certain control lines on the system bus are latched to determine whether an expansion board is driving those lines in response to the I/O read. If so, again it is known that an expansion board is responding to a read from that I/O address. Otherwise, the system then performs a further special I/O read to determine the data bus response time.