Abstract: A cleaning system may be used with a heat exchanger having a core and a fan. The core may include a first core face and an oppositely disposed second core face. The cleaning system may include a plurality of wash nozzles arranged between the first core face and the fan of the heat exchanger. The cleaning system may be used while the heat exchanger is in operation, reducing the downtime of the heat exchanger. A method of retrofitting a heat exchanger with a cleaning system may include arranging a plurality of wash nozzles between the first core face and the fan of the heat exchanger. A method of cleaning a heat exchanger may include arranging a plurality of wash nozzles between the first core face and the fan, supplying a cleaning fluid to the plurality of nozzles, and initiating a cleaning cycle while the heat exchanger is in operation so that the fan assists in moving the cleaning fluid through the core and removing accumulated debris from the second core face.

Abstract: The present invention relates to a mixed oxide of aluminium, of zirconium, of cerium, of lanthanum and optionally of at least one rare-earth metal other than cerium and lanthanum that makes it possible to prepare a catalyst that retains, after severe ageing, a good thermal stability and a good catalytic activity. The invention also relates to the process for preparing this mixed oxide and also to a process for treating exhaust gases from internal combustion engines using a catalyst prepared from this mixed oxide.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: The invention relates to methods and systems taking advantage of bioinformatic investigations to identify candidate signature peptides for quantitative multiplex analysis of complex protein samples from plants, plant parts, and/or food products using mass spectroscopy. Provided are use and methods for selecting candidate signature peptides for quantitation using a bioinformatic approach. Also provided are systems comprising a chromatography and mass spectrometry for using selected signature peptides.

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract: A gas turbine engine includes a fan that includes a plurality of fan blades rotatable about an axis. An on-wing portion includes a compressor section and a combustor that is in fluid communication with the compressor section. A turbine section is in fluid communication with the combustor. A core flow path is arranged within a core nacelle. The fan is arranged upstream from the core flow path. A fan drive gear system module is coupled to the turbine section for rotating the fan about the axis. A connector assembly including first and second members respectively is secured to the on-wing portion and the fan drive gear system module. The first and second members are removably secured to one another by radially extending fasteners. The first members are connected to an on-wing portion of the gas turbine engine and the second members are connected to the fan drive gear system module. The fasteners are accessible through the bypass flow path.

Abstract: A connection assembly for securing a fan drive gear system module within a gas turbine engine includes first and second members removably secured to one another by radially extending fasteners.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: The present disclosure relates generally to a fastener lock for engaging a threaded fastener. The fastener lock defines a discontinuous circular opening therethrough with at least one extending tab extending into the discontinuous circular opening. When a threaded fastener is disposed in the discontinuous circular opening, the at least one extending tab engages the threads of the threaded fastener.

Abstract: A dynamic content controller is configured for communication with one or more data sources. The dynamic content controller comprises an analytics engine and a personalization engine coupled to the analytics engine. The analytic engine is configured to analyze multiple types of disaggregated data collected from the one or more data sources during a current content browsing session. The personalization engine is configured to adapt content to be presented based at least in part on the analysis of the disaggregated data. The adaptation of the content to be presented is performed during the current content browsing session.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract: A system for measuring structural integrity includes a self-contained rapid modal testing trailer that delivers an impact load to a structure being tested and records data resulting from the impact load, and a data processing software that extracts modal parameters of the structure, such as frequencies and mode shapes. The parameters are used to determine anomalous behavior as well as provide experimental data for finite element model calibration.

Abstract: A dynamic content controller is configured for communication with one or more data sources. The dynamic content controller comprises an analytics engine and a personalization engine coupled to the analytics engine. The analytics engine is configured to analyze cultural data collected from the one or more data sources during a current content browsing session. The personalization engine is configured to adapt content to be presented based at least in part on the analysis of the cultural data. The adaptation of the content to be presented is performed during the current content browsing session.

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract: A fixed-variable vane assembly includes a vane that has a fixed airfoil section and a variable airfoil section next to the fixed airfoil section. The variable airfoil section is pivotably mounted at an end thereof in a joint with a variable joint gap that controls a size of an airfoil gap between the fixed airfoil section and the variable airfoil section. A potting material is located in the variable joint gap. The potting material locks the variable joint gap and locks in the size of the airfoil gap.

Abstract: A non-structural multi-part panel including at least two layers, a first layer of foamed material and a second layer applied to at least one side of the first layer, the second layer of cellulosic material.