Patents by Inventor Bartlomiej Jan Pawlak

Bartlomiej Jan Pawlak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10340369
    Abstract: A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 10304833
    Abstract: A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Puneet Harischandra Suvarna, Bipul C. Paul, Ruilong Xie, Bartlomiej Jan Pawlak, Lars W. Liebmann, Daniel Chanemougame, Nicholas V. LiCausi, Andreas Knorr
  • Patent number: 10236379
    Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak
  • Publication number: 20180331213
    Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Applicant: GLOBAL FOUNDRIES INC.
    Inventors: Steven Bentley, Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak
  • Patent number: 10128114
    Abstract: A method of forming a metal-silicon contact is provided. Embodiments include forming a metal layer over a substrate; forming an amorphous silicon (a-Si) capping layer over the metal layer; implanting ions to induce an athermal migration of the a-Si capping layer into the metal layer; and annealing the metal layer and the a-Si capping layer to form a metal silicide layer over the substrate.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: November 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Bartlomiej Jan Pawlak
  • Publication number: 20180269191
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 20, 2018
    Inventors: Luke ENGLAND, Bartlomiej Jan PAWLAK
  • Patent number: 10020395
    Abstract: One illustrative method disclosed herein includes, among other things, forming a trench in a semiconductor substrate, forming a liner semiconductor material above the entire interior surface of the trench, the liner semiconductor material defining a transistor cavity, forming a gate structure that is at least partially positioned within the transistor cavity, and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Jan Pawlak
  • Publication number: 20180053662
    Abstract: A method of texturing a silicon (Si) wafer and the resulting device are provided. Embodiments include forming a mask over an upper surface of a Si wafer; patterning the mask by direct-self assembly (DSA); etching the Si wafer through the patterned mask to form holes in the Si wafer; removing the mask; and etching the holes to form a textured surface in the Si wafer.
    Type: Application
    Filed: August 17, 2016
    Publication date: February 22, 2018
    Inventors: Bartlomiej Jan PAWLAK, Harry J. LEVINSON
  • Publication number: 20180006143
    Abstract: A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.
    Type: Application
    Filed: September 13, 2017
    Publication date: January 4, 2018
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 9793384
    Abstract: One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 9741847
    Abstract: One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a semiconductor substrate, the semiconductor structure comprising a lower source/drain region and an upper source/drain region, wherein the lower source/drain region physically contacts the upper surface of the substrate, forming a counter-doped isolation region in the substrate, forming a metal silicide region in the substrate above the counter-doped isolation region, wherein the metal silicide region is in physical contact with the lower source/drain region, and forming a lower source/drain contact structure that is conductively coupled to the metal silicide region.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 9716177
    Abstract: The device disclosed herein includes, among other things, a substrate made of a first semiconductor material, at least one layer of insulating material positioned above the substrate, a fin structure positioned above the layer of insulating material and the substrate, the fin structure including first, second and third layers of semiconductor material, wherein the semiconductor materials of the first, second and third layers are different than the first semiconductor material, and a gate structure around a portion of the fin structure includes the first, second and third layers of semiconductor material.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: July 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Behtash Behin-Aein, Mehdi Salmani-Jelodar
  • Patent number: 9711644
    Abstract: One illustrative method disclosed herein includes, among other things, forming a liner semiconductor material within a trench, the liner material defining a transistor cavity, and forming spaced-apart source/drain placeholder structures that are at least partially positioned within the transistor cavity, the spaced-apart source/drain placeholder structures defining a gate cavity therebetween where a portion of the liner semiconductor material is exposed within the gate cavity. The method further includes forming a gate structure within the gate cavity and, after forming the gate structure, removing at least a portion of the source/drain placeholder structures to define a plurality of source/drain cavities within the transistor cavity on opposite sides of the gate structure, and forming a source/drain structure in each of the source drain cavities.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 9704962
    Abstract: A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Bartlomiej Jan Pawlak
  • Publication number: 20170179248
    Abstract: A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Jan PAWLAK
  • Publication number: 20170154994
    Abstract: One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a semiconductor substrate, the semiconductor structure comprising a lower source/drain region and an upper source/drain region, wherein the lower source/drain region physically contacts the upper surface of the substrate, forming a counter-doped isolation region in the substrate, forming a metal silicide region in the substrate above the counter-doped isolation region, wherein the metal silicide region is in physical contact with the lower source/drain region, and forming a lower source/drain contact structure that is conductively coupled to the metal silicide region.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 9653593
    Abstract: The present disclosure provides a FinFET device and method of fabricating a FinFET device. The method includes providing a substrate, forming a fin structure on the substrate, forming a gate structure including a gate dielectric and gate electrode, the gate structure overlying a portion of the fin structure, forming a protection layer over another portion of the fin structure, and thereafter performing an implantation process to form source and drain regions.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bartlomiej Jan Pawlak
  • Publication number: 20170098544
    Abstract: A method of forming a metal-silicon contact is provided. Embodiments include forming a metal layer over a substrate; forming an amorphous silicon (a-Si) capping layer over the metal layer; implanting ions to induce an athermal migration of the a-Si capping layer into the metal layer; and annealing the metal layer and the a-Si capping layer to form a metal silicide layer over the substrate.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 6, 2017
    Inventor: Bartlomiej Jan PAWLAK
  • Patent number: 9601379
    Abstract: In one example, the method disclosed herein includes, among other things, forming a sacrificial structure around a plurality of stacked substantially un-doped nanowires at a location that corresponds to the channel region of the device, performing a selective etching process through a cavity to remove a second plurality of nanowires from the channel region and the source/drain regions of the device while leaving a first plurality of nanowires in position, and forming a metal conductive source/drain contact structure in each of the source/drain regions, wherein each of the metal conductive source/drain contact structures is positioned all around the first plurality of nanowires positioned in the source/drain regions.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: March 21, 2017
    Assignees: GLOBALFOUNDRIES Inc., IMEC VZW
    Inventors: Bartlomiej Jan Pawlak, Dmitry Yakimets, Pieter Schuddinck
  • Publication number: 20170077297
    Abstract: One illustrative method disclosed herein includes, among other things, forming a trench in a semiconductor substrate, forming a liner semiconductor material above the entire interior surface of the trench, the liner semiconductor material defining a transistor cavity, forming a gate structure that is at least partially positioned within the transistor cavity, and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 16, 2017
    Inventor: Bartlomiej Jan Pawlak