Abstract: Ultrasonic probes are provided to abate unwanted signal noise. An ultrasonic probe includes a bundle of rods configured to sample data at a first end and propagate a signal encoding the sampled data to a second end. Each of the rods in the bundle of rods has a substantially similar length and a substantially similar diameter. The ultrasonic probe also includes a shell concentrically disposed around the bundle of rods. The shell is configured to pack the bundle of rods together. The shell includes a plurality of grooves configured to abate a prevailing bulk wave sampled by the first end.

Abstract: An ultrasonic transducer is provided. The ultrasonic transducer can be configured for flow metering applications and can include a head mass, a tail mass, and a spanning element joining the head mass with the tail mass. At least one cavity can be created in the head mass, tail mass, or spanning element using additive manufacturing. A method of manufacturing is also provided. The method of manufacturing can include forming a head mass utilizing a first process of additive manufacturing. The method of manufacturing can also include forming a tail mass utilizing a second process or additive manufacturing. The method of manufacturing can further include joining the head mass and the tail mass by a spanning element.

Abstract: A buffer rod for an acoustic measurement device including a ceramic nonmetallic body, a window plate disposed at one longitudinal end of the body, an opposite end of the body configured to interact with a transducer.

Abstract: An ultrasonic transducer is provided. The ultrasonic transducer can be configured for flow metering applications and can include a head mass, a tail mass, and a spanning element joining the head mass with the tail mass. At least one cavity can be created in the head mass, tail mass, or spanning element using additive manufacturing. A method of manufacturing is also provided. The method of manufacturing can include forming a head mass utilizing a first process of additive manufacturing. The method of manufacturing can also include forming a tail mass utilizing a second process or additive manufacturing. The method of manufacturing can further include joining the head mass and the tail mass by a spanning element.

Abstract: A method of designing and forming at least one element of an acoustic transducer. The method includes receiving one or more required operating parameters of the at least one element of the acoustic transducer for an application, iteratively modeling and simulating performance of one or more materials to utilize within the at least one element of the acoustic transducer, iteratively modeling and simulating performance of one or more structures to utilize within the at least one element of the acoustic transducer, identifying at least one material and at least one structure that exhibit predicted performance that at least achieves the one or more required operating parameters of the at least one element of the acoustic transducer for the application, outputting a design of the at least one element of the acoustic transducer, and forming the at least one element of the acoustic transducer via one or more additive manufacturing processes.

Abstract: A method and system for determination of geometric features in an object is provided. The method includes receiving at least one geometric feature response to an ultrasound beam incident on the object. The incident ultrasound beam is produced from one of a plurality of ultrasound transducers. Further, a volumetric representation of the object is generated based on a plurality of object parameters. The volumetric representation of the object and a plurality of transducer parameters are used to generate a predicted beam traversal path in the object. The predicted beam traversal path is utilized to generate a temporal map of predicted time of flight geometric feature response to the ultrasound beam. A position on the volumetric representation of the object is determined as the location of the geometric feature, when the received geometric feature response is equivalent to the predicted time of flight geometric feature response corresponding to the position.

Abstract: A method and system for determination of geometric features in an object is provided. The method includes receiving at least one geometric feature response to an ultrasound beam incident on the object. The incident ultrasound beam is produced from one of a plurality of ultrasound transducers. Further, a volumetric representation of the object is generated based on a plurality of object parameters. The volumetric representation of the object and a plurality of transducer parameters are used to generate a predicted beam traversal path in the object. The predicted beam traversal path is utilized to generate a temporal map of predicted time of flight geometric feature response to the ultrasound beam. A position on the volumetric representation of the object is determined as the location of the geometric feature, when the received geometric feature response is equivalent to the predicted time of flight geometric feature response corresponding to the position.

Abstract: A method and system for determination of geometric features in an object is provided. The method includes receiving at least one geometric feature response to an ultrasound beam incident on the object. The incident ultrasound beam is produced from one of a plurality of ultrasound transducers. Further, a volumetric representation of the object is generated based on a plurality of object parameters. The volumetric representation of the object and a plurality of transducer parameters are used to generate a predicted beam traversal path in the object. The predicted beam traversal path is utilized to generate a temporal map of predicted time of flight geometric feature response to the ultrasound beam. A position on the volumetric representation of the object is determined as the location of the geometric feature, when the received geometric feature response is equivalent to the predicted time of flight geometric feature response corresponding to the position.

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Abstract: In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Abstract: A method and system for determination of geometric features in an object is provided. The method includes receiving at least one geometric feature response to an ultrasound beam incident on the object. The incident ultrasound beam is produced from one of a plurality of ultrasound transducers. Further, a volumetric representation of the object is generated based on a plurality of object parameters. The volumetric representation of the object and a plurality of transducer parameters are used to generate a predicted beam traversal path in the object. The predicted beam traversal path is utilized to generate a temporal map of predicted time of flight geometric feature response to the ultrasound beam. A position on the volumetric representation of the object is determined as the location of the geometric feature, when the received geometric feature response is equivalent to the predicted time of flight geometric feature response corresponding to the position.

Abstract: Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. Embodiments of the invention may comprise of logic, modules or any combination thereof, to detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards its respective memory unit(s), a processor core executing a processor low-power mode, and a processor socket (operatively coupling the processing core and the memory unit) executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit(s) and various components of the memory subsystem.

Abstract: A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.

Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Abstract: In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.