Patents by Inventor Baskaran Ganesan

Baskaran Ganesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Quiescing and de-quiescing point-to-point links
    Patent number: 7761696
    Abstract: Methods and apparatus to quiesce and/or de-quiesce links (such as point-to-point link) in a multi-processor system are described. In one embodiment, one or more bits are modified to indicate the status of quiesce/dequiesce processes.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: July 20, 2010
    Assignee: Intel Corporation
    Inventors: Binata Bhattacharyya, Ling Cen, Rahul Pal, Binoy Balan, Baskaran Ganesan
  • DEVICES, METHODS AND SYSTEMS FOR MEASURING ONE OR MORE CHARACTERISTICS OF A SUSPENSION
    Publication number: 20090158821
    Abstract: A device, method and system for measuring one or more ultrasound parameters of a suspension comprising particles dispersed in a liquid carrier comprising, an immersible devices, comprising, one or more ultrasonic probes; a reflector having staggered reflective; a housing having an opening into the housing to allow the suspension to flow into the space between the probe surface and the reflective surface; an ultrasound wave generator/receiver device; and a signal processing device.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Zongqi Sun, Shridhar Champaknath Nath, Alan M. Williams, Baskaran Ganesan, Mottito Togo, Roger Nordberg, Matthew Allen Radebach
  • Configurable error handling apparatus and methods to operate the same
    Patent number: 7533300
    Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Suresh Marisetty, Baskaran Ganesan, Gautam Bhagwandas Doshi, Murugasamy Nachimuthu, Koichi Yamada, Jose A. Vargas, Jim Crossland, Stan J. Domen
  • Configurable error handling apparatus and methods to operate the same
    Publication number: 20070220332
    Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
    Type: Application
    Filed: February 13, 2006
    Publication date: September 20, 2007
    Inventors: Suresh Marisetty, Baskaran Ganesan, Gautam Doshi, Murugasamy Nachimuthu, Koichi Yamada, Jose Vargas, Jim Crossland, Stan Domen