Patents by Inventor Bassam N. Coury
Bassam N. Coury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190014113Abstract: The present disclosure is directed to secure sensor data transport and processing. End-to-end security may prevent attackers from altering data during the sensor-based security procedure. For example, following sensor data capture execution in a device may be temporarily suspended. During the suspension of execution, sensor interface circuitry in the device may copy the sensor data from a memory location associated with the sensor to a trusted execution environment (TEE) within the device. The TEE may provide a secure location in which the sensor data may be processed and a determination may be made as to whether to grant access to the secure resources. The TEE may comprise, for example, match circuitry to compare the sensor data to previously captured sensor data for users that are allowed to access the secured resources and output circuitry to grant access to the secured resources or to perform activities associated with a security exception.Type: ApplicationFiled: August 29, 2018Publication date: January 10, 2019Applicant: INTEL CORPORATIONInventors: HORMUZD M. KHOSRAVI, BASSAM N. COURY, VINCENT J. ZIMMER
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Publication number: 20180322313Abstract: Embodiments are directed to securing system management mode (SMM) in a computer system. A CPU is configurable to execute first code in a normal mode, and second code in a SSM. A SMM control engine is operative to transition the CPU from the normal mode to the SMM in response to a SMM transition call, and to control access by the CPU in the SMM to data from an originator of the SMM transition call. The access is controlled based on an authorization state assigned to the SMM transition call. An authorization engine is operative to perform authentication of the originator of the SMM transition call and to assign the authorization state based on an authentication result. The CPU in the SMM is prevented from accessing the data in response to the authentication result being a failure of authentication.Type: ApplicationFiled: January 14, 2016Publication date: November 8, 2018Inventors: Jiewen Jacques Yao, Vincent J. Zimmer, Bassam N. Coury
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Patent number: 10069826Abstract: The present disclosure is directed to secure sensor data transport and processing. End-to-end security may prevent attackers from altering data during the sensor-based security procedure. For example, following sensor data capture execution in a device may be temporarily suspended. During the suspension of execution, sensor interface circuitry in the device may copy the sensor data from a memory location associated with the sensor to a trusted execution environment (TEE) within the device. The TEE may provide a secure location in which the sensor data may be processed and a determination may be made as to whether to grant access to the secure resources. The TEE may comprise, for example, match circuitry to compare the sensor data to previously captured sensor data for users that are allowed to access the secured resources and output circuitry to grant access to the secured resources or to perform activities associated with a security exception.Type: GrantFiled: September 19, 2017Date of Patent: September 4, 2018Assignee: Intel CorporationInventors: Hormuzd M. Khosravi, Bassam N. Coury, Vincent J. Zimmer
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Publication number: 20180027679Abstract: Examples may include sleds for a rack in a data center including physical compute resources and memory for the physical compute resources. The memory can be disaggregated, or organized into near and far memory. A first sled can comprise the physical compute resources and a first set of physical memory resources while a second sled can comprise a second set of physical memory resources. The first set of physical memory resources can be coupled to the physical compute resources via a local interface while the second set of physical memory resources can be coupled to the physical compute resources via a fabric.Type: ApplicationFiled: March 31, 2017Publication date: January 25, 2018Applicant: INTEL CORPORATIONInventors: MARK A. SCHMISSEUR, BASSAM N. COURY
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Publication number: 20180026981Abstract: The present disclosure is directed to secure sensor data transport and processing. End-to-end security may prevent attackers from altering data during the sensor-based security procedure. For example, following sensor data capture execution in a device may be temporarily suspended. During the suspension of execution, sensor interface circuitry in the device may copy the sensor data from a memory location associated with the sensor to a trusted execution environment (TEE) within the device. The TEE may provide a secure location in which the sensor data may be processed and a determination may be made as to whether to grant access to the secure resources. The TEE may comprise, for example, match circuitry to compare the sensor data to previously captured sensor data for users that are allowed to access the secured resources and output circuitry to grant access to the secured resources or to perform activities associated with a security exception.Type: ApplicationFiled: September 19, 2017Publication date: January 25, 2018Applicant: Intel CorporationInventors: HORMUZD M. KHOSRAVI, BASSAM N. COURY, VINCENT J. ZIMMER
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Publication number: 20180007791Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.Type: ApplicationFiled: September 12, 2017Publication date: January 4, 2018Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
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Patent number: 9832876Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.Type: GrantFiled: December 18, 2014Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
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Patent number: 9769169Abstract: The present disclosure is directed to secure sensor data transport and processing. End-to-end security may prevent attackers from altering data during the sensor-based security procedure. For example, following sensor data capture execution in a device may be temporarily suspended. During the suspension of execution, sensor interface circuitry in the device may copy the sensor data from a memory location associated with the sensor to a trusted execution environment (TEE) within the device. The TEE may provide a secure location in which the sensor data may be processed and a determination may be made as to whether to grant access to the secure resources. The TEE may comprise, for example, match circuitry to compare the sensor data to previously captured sensor data for users that are allowed to access the secured resources and output circuitry to grant access to the secured resources or to perform activities associated with a security exception.Type: GrantFiled: September 25, 2015Date of Patent: September 19, 2017Assignee: INTEL CORPORATIONInventors: Hormuzd M. Khosravi, Bassam N. Coury, Vincent J. Zimmer
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Publication number: 20170249250Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: March 13, 2017Publication date: August 31, 2017Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
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Publication number: 20170093852Abstract: The present disclosure is directed to secure sensor data transport and processing. End-to-end security may prevent attackers from altering data during the sensor-based security procedure. For example, following sensor data capture execution in a device may be temporarily suspended. During the suspension of execution, sensor interface circuitry in the device may copy the sensor data from a memory location associated with the sensor to a trusted execution environment (TEE) within the device. The TEE may provide a secure location in which the sensor data may be processed and a determination may be made as to whether to grant access to the secure resources. The TEE may comprise, for example, match circuitry to compare the sensor data to previously captured sensor data for users that are allowed to access the secured resources and output circuitry to grant access to the secured resources or to perform activities associated with a security exception.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Applicant: INTEL CORPORATIONInventors: HORMUZD M. KHOSRAVI, BASSAM N. COURY, VINCENT J. ZIMMER
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Patent number: 9600416Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: September 30, 2011Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Publication number: 20160239460Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.Type: ApplicationFiled: November 27, 2013Publication date: August 18, 2016Inventors: Dimitrios Ziakas, Bassam N. Coury, Mohan J. Kumar, Murugasamy K. Nachimuthu, Thi Dang, Russell J. Wunderlich
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Publication number: 20160183374Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
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Patent number: 9317429Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: September 30, 2011Date of Patent: April 19, 2016Assignee: Intel CorporationInventors: Raj K Ramanujan, Dimitrios Ziakas, David J Zimmerman, Mohan J Kumar, Muthukumar P Swaminathan, Bassam N Coury
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Publication number: 20140129767Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: September 30, 2011Publication date: May 8, 2014Inventors: Raj K Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn N. Hinton
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Publication number: 20130275682Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: September 30, 2011Publication date: October 17, 2013Inventors: Raj K. Ramanujan, Dimitrios Ziakas, David J. Zimmerman, Mohan J. Kumar, Muthukumar P. Swaminathan, Bassam N Coury
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Patent number: 7162560Abstract: A system that may optionally be partitioned into multiple domains is disclosed. Each domain is capable of independently powering on, executing a firmware program, and loading an operating system, including a legacy operating system, as well as running an application program that is distinct from programs running on another domain. Interrupts, including boot interrupts, reset handlers, and inter-chassis communications are initialized differently, depending on whether the system is to be partitioned or not. The cost of redundant hardware and/or firmware is substantially avoided, yet the system fully supports multiple domains.Type: GrantFiled: December 31, 2003Date of Patent: January 9, 2007Assignee: Intel CorporationInventors: Billy K. Taylor, Mohan J. Kumar, Wilson E. Smoak, David J. O'Shea, Bassam N. Coury, Priscilla Lam, Tom Slaight