CPU package substrates with removable memory mechanical interfaces
Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
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Embodiments generally relate to package substrates and, more specifically, central processing unit (CPU) package substrates with removable memory mechanical interfaces.
BACKGROUNDAn increasing demand for higher performance computers has driven a greater effort to increase the performance of internal device components. The performance of a computer's CPU is highly dependent upon the bandwidth and capacity of memory devices that are accessible to the CPU. The bandwidth and capacity limitations of such memory consequently limit the performance of the CPU. Thus, industry leaders are motivated to increase the accessibility of memory devices to a CPU.
According to one approach, memory devices may be attached directly to the CPU package substrate rather than on the motherboard. Although a variety of memory devices can be integrated on the CPU package substrate, the memory devices cannot be reconfigured after package assembly.
The package assembly process includes attaching a CPU and memory devices onto a CPU package substrate. Conventional methods integrate memory devices on the CPU package substrate by soldering them directly on the CPU package substrate during the package assembly process. A conventional CPU package substrate 100 is illustrated in
As technology continues to develop, the marketplace becomes more segmented with varying requirements of memory capacity and bandwidth needs. Additionally, customers increasingly look for custom memory arrangements for their specific applications. Due to the inability to reconfigure the memory device arrangement after CPU package assembly, current producers of these CPU package assemblies are having to generate numerous model variations to keep up with customer preferences. Having numerous model variations can be cumbersome, time consuming, and expensive to maintain.
CPU Package substrates with configurable/removable memory are disclosed. In the following description, numerous specific details are set forth, such as specific integration regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features are not described in detail in order to not necessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
1.0 CPU Package Substrate with Removable Memory Mechanical Interfaces
Embodiments of the present invention disclose configurable CPU package substrates with removable memory mechanical interfaces that enable memory devices to be easily removed and re-attached. In one embodiment of the invention, a configurable CPU package substrate includes a processing device interface and a memory device electrical interface. The processing device interface and memory device electrical interface couple to a processing device (e.g., a CPU) and a memory device (e.g., a DRAM chip), respectfully. In an embodiment, the configurable CPU package substrate further includes a removable memory mechanical interface. The removable memory mechanical interface allows attachment and detachment of a memory device after CPU package assembly. When attached by the removable memory mechanical interface, the memory device is physically and electrically coupled to the CPU package substrate.
In embodiments, the removable memory mechanical interface is a socket within which a memory device is inserted to couple to the CPU package substrate. Although the removable memory mechanical interface is a socket in many embodiments, the removable memory mechanical interface may be implemented as other structures as well. For instance, the removable memory mechanical interface may be a set of press-fit holes within which a corresponding set of alignment pins are inserted. The removable memory mechanical interface may also be a set of alignment pins designed to fit within press-fit holes on a memory device substrate. Additionally, the removable memory mechanical interface may be a spring-loaded clip that clips a memory device onto the CPU package substrate.
Despite their numerous variations, the removable memory mechanical interfaces in embodiments disclosed herein commonly enable CPU package substrates to be easily reconfigured with different memory devices after package assembly. During CPU package assembly, electrical devices such as a CPU are mounted on the CPU package substrate. Instead of permanently mounting memory devices directly onto the CPU package substrate as conventionally done, removable memory mechanical interfaces are formed or mounted on the CPU package substrate during package assembly, thus forming a configurable CPU package substrate. A processing device may then be attached to the configurable CPU package substrate, thereby forming a memory-configurable CPU package. Memory devices may then be attached to the removable memory mechanical interfaces before or after sending the memory-configurable CPU package to customers. After receiving the memory-configurable CPU package, the customer may reconfigure the memory arrangement as desired.
For instance, the customer may remove existing memory devices and reattach new memory devices as an upgrade. Configurable CPU package substrates therefore enable reconfiguration of memory devices after the package assembly process. Enabling reconfiguration after the package assembly process has several possible advantages. For example, enabling reconfiguration after package assembly increases the versatility of the CPU package substrate. A single CPU package substrate may thus be used for several different applications, as opposed to having several assembled CPU package substrates where each one is tailored for a different application. Additionally, customers can reconfigure the memory devices on their own, without having to send the memory-configurable CPU package back to the manufacturer or without having to use expensive tools.
Embodiments of the invention also enable manufacturers to tailor products to customer needs in a cost effective way. For instance, instead of having to solder memory devices onto a packaged substrate, memory devices may be merely pressed into sockets on the CPU package substrate. Not having to perform a soldering process increases throughput and decreases cost. Additionally, ease of reconfiguration may eliminate the possibility of having CPU package assemblies with undesirable memory configurations.
Additionally, embodiments of the invention help the quality assurance testing process. For instance, memory devices may be removed during testing. Accordingly, when a memory failure occurs, the failure is easily attributed to the internal memory within the CPU device. There is little uncertainty as to which memory (internal or external) is failing. By subsequently adding one memory device at a time and performing testing procedures, each memory device can be tested separately. For instance, if it is known that the internal memory is functioning correctly, failures during testing when only one external memory device is attached may clearly indicate that the failure is occurring in the single external memory device. By enabling this testing strategy, removable memory mechanical interfaces increase throughput and decrease production cost.
The processing device interface 202 may be any suitable interconnection structure for coupling to a processing device (e.g., a multicore processor chip). For instance, processing device interface 202 may be an LGA having a plurality of rows N and columns M organized in an N×M array. In such arrangements, the processing device interface 202 may couple to a processing device (not shown) by an array of solder joints via, e.g., flip-chip bonding. Alternatively, the processing device interface 202 may be an array of pads arranged in a frame-like pattern. For example, the frame-like pattern of pads may surround a region with no pads. In such instances, the processing device interface 202 may couple to a processing device by a plurality of wires via wire bonding.
The memory device electrical interface 206 may be an electrical interconnection arrangement for communicatively coupling to a memory device. For instance, memory device electrical interface 206 may be an LGA organized on the CPU package substrate 204 in an N×M arrangement or any other array formation. The memory device electrical interface 206 may couple directly to a memory device substrate or to electrical connections integrated into a removable memory mechanical interface as will be disclosed further herein. The removable memory mechanical interface may be disposed in regions 208 around the memory device electrical interface 206. Accordingly, regions 208 are regions where a removable memory mechanical interface may be located. In an embodiment, regions 208 extend proximately to the memory device electrical interface. Regions 208 may extend to areas on the configurable CPU package substrate 204 directly beside the memory device electrical interface 206 as well as areas directly above the memory device electrical interface 206.
According to embodiments of the invention, the memory device 205 is attachable to and detachable from the removable memory mechanical interface. In embodiments, a separate tool is not needed to attach or detach the memory device to/from the mechanical interface. For instance, the memory device can be detached from the memory device mechanical interface in region 208 by pulling the memory device out of the removable memory mechanical interface. Further, a separate memory device may be attached to the removable memory mechanical interface by pushing the memory device into the removable memory mechanical interface. The pulling and pushing may be performed by hand such that no separate tool is needed. Enabling installation of memory devices by hand allows the configurable CPU package substrate 204 to be substantially versatile. Memory devices may be installed after fabrication of the memory-configurable CPU package, thereby allowing customers to easily customize the performance of the memory-configurable CPU package according to their specific applications.
The removable memory mechanical interface may be any suitable structure for mechanically attaching and detaching a memory device to/from the CPU package substrate such that insertions and removals are easily repeated. Examples include sockets, press fit holes, alignment pins and a clip. Some basic examples of these are reviewed immediately below.
Alternatively from a socket 302, as observed in
Further alternatively, the removable memory mechanical interface may be a set of alignment pins 306 as illustrated in
Further still alternatively, the removable memory mechanical interface may be a spring-loaded clip 308 as illustrated in
Conceivably a removable memory mechanical interface may be implemented by combining two or more types of mechanical interfaces such as two or more of the types of mechanical interfaces discussed above with respect to
1.1 Socket Embodiments
The removable memory mechanical interface may be formed of various structures, several of which may be different variations of sockets. To better disclose these variations, the following embodiments illustrate a configurable CPU package substrate with the various sockets as the removable memory mechanical interfaces. The various removable memory mechanical interfaces may be located within the region 208 as disclosed herein with respect to
1.1.1 Sliding Rail Socket
In an embodiment, the removable memory mechanical interface is a sliding rail socket.
An exemplary sliding rail socket counterpart 401 for the sliding rail socket 402 is illustrated in
With reference to
Referring now to
As shown in
In the embodiment depicted in
The sliding rail socket 402 may include a window 412. In an embodiment, the window 412 is an opening 412 of the sliding rail socket 402 that allows the memory device 205 to slide within it, as shown in
In embodiments, the static friction between the sliding grooves 410 and the sliding rail socket counterpart 401 hold the memory device 205 in place. Accordingly, a force with a magnitude greater than the static frictional force may thereby remove the memory device 205 from the sliding rail socket 402 of the configurable CPU package substrate 200. A new sliding rail socket counterpart 401 with a new memory device 205 may then replace the old counterpart 401 and attach to the sliding rail socket 402. In embodiments, a separate tool is not required to remove the memory device 205 from the sliding rail socket 402.
1.1.2 Multi-Edge Socket
Other than a sliding rail socket, the removable memory mechanical interface may be a multi-edge socket. For instance, the removable memory mechanical interface may be a double edge socket or a full edge pin grid array socket, as further discussed herein.
1.1.2.1 Double Edge Socket
A detailed front and back perspective view of the double edge socket 502 is illustrated in
In embodiments, the opening 504 contains an array of I/O connections 514 for coupling to external structures. In an embodiment, the array of I/O connections 514 is an array of contacts, such as an array of pads or cantilever pins. The array of I/O connections 514 may be disposed on a bottom-inner surface of the opening 504. Additionally, in an embodiment, the opening 504 contains a second array of I/O connections (not shown). The second array of I/O connections may be disposed on the top-inner surface of the opening 504. The array of I/O connections 514 may be oriented along an insertion direction to prevent electrical shorting between adjacent contacts during installation. In an embodiment, the insertion direction is at an angle half of the offset angle from the first or second portion 506/508. Further illustration of the insertion direction is shown in
The array of I/O connections 514 may have a contact pitch designed to maximize the number of contacts while assuring each contact has sufficient surface area for forming electrical connections. In an embodiment, the contact pitch may range between 0.3 to 0.5 mm. In a particular embodiment, the array of I/O connections 514 has a contact pitch of about 0.4 mm. Accordingly, for a socket 520 containing bottom- and top-inner array of I/O connections 514, double edge socket 502 may have a total of approximately 160 pads. Additionally, a contact density of approximately 5 contacts per mm is achievable.
Both arrays of I/O connections 514 may be electrically coupled to corresponding arrays of wire connections 520 located behind the double edge socket 502, as illustrated in
The memory device substrate 540 also includes a single connection interface 522. Single connection interface 522 may continuously extend across two adjacent edges, such as edges 505A and 505B. Accordingly, the single connection interface 522 may form an L-shaped profile along edges 505A and 505B. In an embodiment, the single connection interface 522 includes an array of pads 524 that extend to the very edge of the memory device substrate 540. The array of pads 524 may have a contact pitch that corresponds to the double edge connector 502. For instance, the array of pads 524 may have a contact pitch of approximately 0.4 mm, thus forming an array of pads 524 containing approximately 160 pads.
In embodiments, each pad of the array of pads 524 is aligned with an insertion direction 515. The insertion direction 515 may be the direction at which the double edge socket counterpart 503 inserts into the double edge socket 502 to prevent shorting between each pad of the array of pads 524. In an embodiment, the insertion direction 515 is at an angle 513 that is half of the separation angle 511. Accordingly, each pad of the array of pads 524 is aligned in a direction at an angle 513 that is half of the separation angle 511. In an embodiment where the separation angle is 90 degrees, each pad of the array of pads 524 is aligned in a direction at an angle of 45 degrees from edge 505A. In embodiments, each pad of the array of pads 524 is aligned in the same direction as the array of I/O connections 514.
Although
The memory device substrate 540 may also include beveled edges 518. The beveled edges 518 may be located on corners of the memory device substrate 540 where ends of the single connection interface 522 are located. For instance, the beveled edges 518 may be located at the corners between edges 505B and 505C, as well as edges 505A and 505D. The beveled edges 518 may be oriented along the insertion direction 515. Accordingly, in an embodiment, the beveled edges 518 are parallel to the pads 524. As will be discussed further herein with respect to
As shown in
In embodiments, the static friction between the array of pads 524 and the array of I/O connections 514 may hold the memory device 205 in place. Accordingly, a force with a magnitude greater than the static frictional force may thereby remove the memory device 205 from the double edge socket 502 of the configurable CPU package substrate 200. A new double edge socket counterpart 503 with a new memory device 205 may then replace the old counterpart 503 and attach to the double edge socket 502. In embodiments, a separate tool is not required to remove the memory device 205 from the double edge socket 502.
1.1.2.2 Full Edge Pin Grid Array Socket
A more detailed view of the full edge pin grid array socket 602 is illustrated in
With reference to
The connection interfaces 622A and 622B may each include an array of pads 624 that extend to the edge of the memory device substrate 640. A mirrored array of pads (not shown) may also be disposed on the underside of the memory device substrate 640. The array of pads 624 may have a contact pitch that maximizes the number of pads while maintaining sufficient surface area to form robust electrical connections. For instance, the array of pads 624 may have a contact pitch of approximately 0.4 mm, thus forming a connection interface 622 containing approximately 160 pads. Given that there are two connection interfaces 622A and 622B, the memory package 640 may thus have a total of approximately 320 pads.
Again, similar to the double edge socket counterpart 503, each pad of the array of pads 624 on the memory device substrate 640 of the device portion 603 is aligned with an insertion direction 615. The insertion direction 615 may be the direction at which the interconnection portions 607 assemble with the device portion 603 to prevent shorting between each pad of the array of pads 624. The insertion direction 615 may be at an angle 613 that is half of the separation angle 611. Thus, each pad of the array of pads 624 may be aligned at an angle 613 that his half of the separation angle 611.
Beveled edges 618 may be located on corners of the memory device substrate 640 where ends of the connection interfaces 622A and 622B are located. Additionally, the beveled edges 618 may be oriented along the insertion direction 615. Accordingly, in an embodiment, the beveled edges 618 are parallel to the pads 624. The beveled edges 618 assist in assembling the interconnection portions 607 with the device portion 603, as will be discussed herein with respect to
With reference now to
In
Once the full edge pin grid array socket counterpart 621 is assembled, it may then be attached to the full edge pin grid array socket 602.
In embodiments, the static friction between the connecting pins 620 and the openings 606 may hold the memory device 205 in place. Accordingly, a force with a magnitude greater than the static frictional force may thereby remove the memory device 205 from the full edge pin grid array socket 602 of the configurable CPU package substrate 200. A new device portion 603 with a new memory device 205 may then replace the old device portion 603 and attach to the full edge pin grid array socket 602. In embodiments, a separate tool is not required to detach and reattach the memory device 205 from the full edge pin grid array socket 602.
1.1.3 Low Insertion Force Socket
According to embodiments of the invention, the removable memory mechanical interface may also be a low insertion force socket.
In embodiments, each opening of the array of openings 704 may contain a contact pin 708. The contact pin 708 may couple to an interconnection structure of a low insertion force socket counterpart, as will be discussed herein. The structural profile of the contact pin 708 is illustrated in
With reference now to
An exemplary method of attaching the memory device 205 to the removable memory mechanical interface is illustrated in
In
In embodiments, the downward force generated by the connecting pin 708 may hold the memory device 205 in place. Accordingly, a force with a magnitude greater than the downward force may thereby remove the memory device 205 from the low insertion force socket 702 of the configurable CPU package substrate 200. A new low insertion force socket counterpart 703 with a new memory device 205 may then replace the old low insertion force socket counterpart 703 and attach to the low insertion force socket 702. In embodiments, a separate tool is not required to remove the memory device 205 from the low insertion force socket 702.
1.1.3.1 Flexible Cable Variant of the Low Insertion Force Socket Counterpart
According to embodiments of the invention, the low insertion force socket 702 and counterpart 703 may have variant designs. For instance, the low insertion force socket counterpart 703 may include a flex cable to form a flex cable counterpart 803, as depicted in the embodiment illustrated in
With reference now to
In
In embodiments, the memory device 205 is held in place by the low insertion force socket 802 as well as the mechanical fastener that attaches the memory device 205 to the heat sink 820. Accordingly, unclipping the mechanical fastener, removing the heat sink 820, and pulling the flex cable counterpart 803 away from the socket 802 with a force greater than the downward force generated by the pins within the socket 802 may thereby remove the memory device 205 from the configurable CPU package substrate 200. A new flex cable counterpart 803 with a new memory device 205 may then replace the old flex cable counterpart 803 and attach to the low insertion force sockets 802 of the configurable CPU package substrate 200.
1.1.3.2 Flexible Cable Variant of the Low Insertion Force Socket
In another example, the low insertion force socket 702 may include a flex cable to form a flex cable socket 902, as depicted in the embodiment illustrated in
In
Given the flexible nature of the flex cable 904, the flex cable socket 902 may be arranged in a wide range of positions. For instance, the low insertion force socket 702 of the flex cable socket 902 may be arranged vertically above the configurable CPU package substrate 200. Accordingly, the flex cable socket 902 may allow a memory device 205 to be attached to a heat sink, as will be discussed further herein.
A low insertion force socket counterpart 903 is illustrated in
With reference to
Given the flexible nature of the flex cable 904, the flex cable socket 902 may be arranged in a wide range of positions. For instance, the flex cable socket 902 may be arranged such that the low insertion force socket 702 is vertically positioned and disposed above the configurable CPU package substrate 200 as illustrated in
In
In embodiments, the memory device 205 is held in place by the flex cable sockets 902 as well as the mechanical fastener that attaches the memory device 205 to the heat sink 920. Accordingly, unclipping the mechanical fastener and pulling the low insertion force counterpart 903 away from the low insertion force socket 702 with a force greater than the downward force generated by the pins within the socket 702 may thereby remove the memory device 205 from the flex cable socket 902 of the configurable CPU package substrate 200. A new low insertion force counterpart 903 with a new memory device 205 may then replace the old low insertion force counterpart 903 and be attached to the flex cable socket 902.
1.1.4 “Zero” Insertion Force Socket
According to embodiments of the invention, the removable memory mechanical interface may also be a “zero” insertion force socket. The zero insertion force socket has very slight if any resistance against insertion of a counterpart which slides horizontally into the removable memory mechanical interface as will be discussed further herein.
In an embodiment, each socket 1002A and 1002B of the zero insertion force socket 1002 includes a housing structure 1006A/1006B and an opening 1004A/1004B disposed within the respective housing structure 1006A/1006B. The zero insertion force socket 1002 enables a memory device (not shown) to be removable from the configurable CPU package substrate 200. The zero insertion force socket 1002 may be electrically coupled to a memory device electrical interface (not shown) disposed on the substrate 200 below the socket 1002. A detailed view of the zero insertion force socket 1002B is illustrated in
In embodiments, the housing structure 1006B includes an opening 1004B. The opening 1004B may be disposed on a side of the housing structure 1006B such that an interconnection structure may insert laterally into the housing structure 1006B. In an embodiment, the opening 1004B is a single, elongated opening that spans across a portion, if not a majority, of the length 1009 of the socket 1002B. Alternatively, the opening 1004B may be a plurality of openings disposed across at least a portion of the length 1009. A plurality of contacts 1012 may be disposed within the opening 1004B. Each contact 1012 may be disposed on the top- and bottom-inner wall of the opening 1004B so that each contact 1012 may couple to at least two sides of an interconnection structure. In an embodiment, an array of connectors 1010 are disposed on a side of the housing structure 1006B opposite of the opening 1004. The array of connectors 1010 may couple the socket 1002B to the configurable CPU package substrate 200. Specifically, the array of connectors 1010 may couple the plurality of contacts 1012 to the memory device electrical interface (not shown) of the configurable CPU package substrate 200.
With reference now to
The zero insertion force socket counterpart 1003 also includes a pair of flex cables 1014A and 1014B. The pair of flex cables 1014A and 1014B may be attached to the memory device substrate 1040 at one end and have a connection structure 1016A and 1016B at the opposite end, respectively. The connection structures 1016A and 1016B may each have an array of interconnects 1018. In an embodiment, the array of interconnects 1018 is an array of pads or a plurality of pins. Flex cables 1014A and 1014B allow the connection structures 1016A and 1016B to insert into the opening 1004 of the zero insertion force sockets 1002 to form an electrical connection, as will be discussed further herein with respect to
To attach the zero insertion force socket counterpart 1003, connection structure 1016A may insert into opening 1004A of the zero insertion force socket 1002A as shown in
As further illustrated in
In
Although
In an embodiment, utilizing the zero insertion force socket 1002 minimizes the overall package height, as shown in
A thickness 1026 of the zero insertion force socket assembly 1005 depends on the thicknesses of the counterpart 1003 and the socket 1002. For instance, the thickness 1026 of the zero insertion force socket assembly 1005 is the greater of the counterpart thickness and the socket thickness. In an embodiment, the thickness of the counterpart 1003 ranges between 1 to 1.5 mm. The thickness of the socket 1002 ranges between 3 to 3.5 mm. Thus, in such an embodiment, the thickness of the zero insertion force socket assembly 1005 is approximately 3 to 3.5 mm. Given the small thickness 1026, the separation gap 1024 between the heat sink 1020 and the configurable substrate 200 may be minimized. In an embodiment, the separation gap 1024 is between approximately 5 to 8 mm. By minimizing the separation gap 1024, the overall package size may be minimized as well.
In embodiments, the memory device 205 is held in place by the zero insertion force socket 1002. Accordingly, pulling up the locking levers 1008A and 1008B unlocks the socket 1002, which enables the memory device 205 to be removed from the zero insertion force socket 1002 of the configurable CPU package substrate 200. A new zero insertion force counterpart 1003 with a new memory device 205 may then replace the old zero insertion force counterpart 1003 and be attached to the zero insertion force socket 1002.
1.1.5 Frame Socket
In addition to the sockets already discussed herein, the removable memory mechanical interface may be a frame socket 1102 as illustrated in
In embodiments, the frame socket 1102 allows a memory device 205 to be removable from the configurable CPU package substrate 200. Additionally, the frame socket 1102 may allow a memory device 205 to be coupled to the memory device electrical interface 206 by simply placing the memory device 205 into the frame socket 1102. In an embodiment, an intermediate structure is used to facilitate attachment of the memory device 205 to the memory device electrical interface 206. The intermediate structure may be any suitable interconnection structure capable of physically and electrically coupling two structures to one another. For instance, the intermediate structure may be a reflowable grid array (RGA), which is discussed in
In an embodiment, the RGA substrate 1107 includes a pair of internal heater grids: top internal heater grid 1110 and bottom internal heater grid 1112. The internal heater grids 1110 and 1112 are each formed of an array of wires constructed from a conductive material, such as a metal. The array of wires may generate heat when a current is flowed through them. In an embodiment, the internal heater grids 1110 and 1112 are embedded within the RGA substrate 1107, but proximate to the top and bottom surfaces 1109 and 1111. For instance, the top internal heater grid 1110 may be placed proximate to the top surface 1109, and the bottom internal heater grid 1112 may be placed proximate to the bottom surface 1111. In an embodiment, the heater grids 1110 and 1112 are placed a distance of between 1 to 3 mm, e.g., approximately 2 mm, away from their respective arrays of solder balls. Accordingly, the close proximity to the surfaces allows the heater grids 1110 and 1112 to reflow the array of solder balls disposed on the corresponding surfaces when they generate heat. Although
In embodiments, the edges 1105 of the memory device substrate 1140 are contacted with the inner surface 1123 of the frame socket 1102. In such embodiments, the frame socket 1102 helps the memory device substrate 1140 align with the RGA 1104. In addition to the memory device substrate 1140, the RGA 1104 may also have edges that make contact with the inner surface 1123. Accordingly, the frame socket 1104 may help the RGA 1104 align with the memory device electrical interface 206 as well.
A notch 1103 may be disposed within an edge of the frame socket 1102. In embodiments, the notch 1103 is an opening formed within a side of the socket 1102 that allows access to the RGA 1104 after it is attached to the memory device electrical interface 206. Thus, the RGA 1104 and/or the memory device 205 may be removed after attachment. For instance, to remove the memory device 205 from the socket 1102, the top and/or bottom solder balls 1106/1108 may be reflowed and the memory device 205 may be pulled off of the configurable CPU package substrate 200 when the solder balls 1106/1108 are still in liquid form. In an embodiment, current is flowed through the top and/or bottom internal heater grids 1110/1112 to reflow the solder balls 1106/1108 while the memory device 205 is being pulled off. Accordingly, the RGA 1104 enables the memory device 205 to be removable after attachment. In an embodiment, a new RGA 1104 with a new set of solder balls 1106/1108 may be used to attach a new memory device 205 to the frame socket 1102.
The frame socket package assembly 1120 may be formed by at least three methods. Each of the at least three methods are illustrated in exemplary embodiments shown in
In an embodiment, the RGA 1104, along with the memory device 205 and memory device substrate 1140, is then placed within the frame socket 1102. An edge 1105 of the RGA 1104 may slide against an inner surface 1123 of the frame socket 1102 to align the bottom array of solder balls 1108 with the memory device electrical interface 206 (e.g., an array of pads). Once the bottom solder balls 1108 are placed on corresponding pads of the memory device electrical interface 206, the bottom solder balls 1108 may be reflowed to attach the memory device 205 to the configurable CPU package substrate 200. In an embodiment, reflowing the bottom array of solder balls 1108 is performed by flowing current through only the bottom internal heater grid 1112. For instance, a switch (not shown) may be activated to allow current to flow through the bottom internal heating grid 1112. Accordingly, the RGA 1104 may only have one internal heater grid—the bottom internal heater grid 1112.
Rather than pre-attaching the RGA 1104 to the memory device substrate 1140, the RGA 1104 may be pre-attached to the configurable CPU package substrate 200 instead.
To attach the memory device 205 to the configurable CPU package substrate 200, the memory device substrate 1140 may be lowered onto the top array of solder balls 1106. In embodiments, edges 211 of the memory device substrate 1140 slide against the inner surface 1123 of the frame socket 1102. Sliding against the inner surface 1123 aligns the memory device substrate 1140 to the RGA 1104. Specifically, the array of interconnection structures 1116 may be aligned with the top array of solder balls 1106. Once the interconnection structures 1116 are placed on the top array of solder balls 1106, the top array of solder balls 1106 may be reflowed to attach the memory device substrate 1140 to the RGA 1104. Accordingly, the memory device 205 may therefore be coupled to the configurable CPU package substrate 200. In an embodiment, reflowing the top array of solder balls 1106 is performed by flowing current through only the top internal heater grid 1110. For instance, a switch (not shown) may be activated to allow current to flow through the top internal heating grid 1110. Accordingly, the RGA 1104 may only have one internal heater grid—the top internal heater grid 1110.
Rather than pre-attaching the RGA 1104 to either the memory device substrate 1140 or the configurable CPU package substrate 200, the RGA 1104 may be attached to both substrate 1140 and 200 simultaneously.
In the aforementioned embodiments, the memory device 205 is attached to the configurable CPU package substrate 200 by the reflowed solder balls 1106/1108 of the RGA 1104. Accordingly, reflowing the solder balls 1106/1108 and pulling the memory device 205 away from the socket 1102 when the solder balls 1106/1108 are in liquid form may thereby remove the memory device 205 from the frame socket 1102 of the configurable CPU package substrate 200. A new memory device 205 and memory device substrate 1140 may then replace the old memory device 205 and memory device substrate 1140 and be attached to the frame socket 1102 by a new RGA 1104.
1.2 Set of Press Fit Holes Embodiment
Although the removable memory mechanical interface may be formed as sockets in several embodiments, in alternative embodiments, the removable memory mechanical interface may be formed as a set of press fit holes as shown in
The press fit hole counterpart 1203 may also include a set of attachment pins 1206. The attachment pins 1206 may be disposed on the bottom surface of the memory device substrate 1240. In an embodiment, the set of attachment pins 1206 is arranged to correspond with the set of press fit holes 1202. Accordingly, each attachment pin 1206 may correspond to a respective press fit hole 1202. In a particular embodiment, the attachment pins 1206 are disposed near the corners of the memory device substrate 1240. The attachment pins 1206 may also include a tapered end 1207. The tapered end 1207 may help guide the attachment pins 1206 into the press fit holes 1202, as will be discussed further herein.
Additionally, the press fit hole counterpart 1203 may also include an array of interconnection structures 1204. The array of interconnection structures 1204 may be disposed on the bottom of the memory device substrate 1240 and within the separation frame 1208. In an embodiment, the interconnection structures 1204 are cantilever pins. Each interconnection structure of the array of interconnection structures 1204 may correspond to respective pads of the memory device electrical interface 206.
The interconnection structures 1204 may protrude below the separation frame 1208 as shown in
In addition to the interconnection structures 1204, the attachment pins 1206 may also protrude below the separation frame 1208. The attachment pins 1206 may protrude a distance 1214 below the bottom 1212 of the separation frame 1208. In embodiments, the attachment pins 1206 protrude farther than the interconnection structures 1204. Accordingly, the distance 1214 may be greater than the distance 1210. Having the attachment pins 1206 protrude farther than the interconnection structures 1204 allows the attachment pins 1206 to insert into the set of press fit holes 1202 while allowing the interconnection structures 1204 to make contact with the memory device electrical interface 206. In an embodiment, the distance 1214 is at least 2 mm. In a particular embodiment, the distance 1214 is between 2-4 mm.
To attach the press fit hole counterpart 1203, the set of attachment pins 1206 may be pushed toward the set of press fit holes 1202, as shown in
As shown in
In an embodiment, the diameter of the attachment pins 1206 above the tapered ends 1207 is substantially equal to, if not slightly larger than, the diameter of the press fit holes 1202. Accordingly, when the attachment pins 1206 are inserted into the press fit holes 1202, the attachment pins 1206 fit snugly into the press fit holes 1202, thereby creating sufficient static friction to keep the counterpart 1203 in place. Additionally, a heat sink (not shown) may also apply enabling force (e.g., downward force) to keep the counterpart 1203 attached.
In embodiments, the memory device 205 is attached to the configurable CPU package substrate 200 by the static frictional force created between the set of press fit holes 1202 and the set of attachment pins 1206. Accordingly, pulling the press fit hole counterpart 1203 away from the configurable CPU package substrate 200 with a force greater than the static frictional force may thereby remove the memory device 205 from the set of press fit holes 1202 of the configurable CPU package substrate 200. A new press fit hole counterpart 1203 with a new memory device 205 may then replace the old press fit hole counterpart 1203 with the old memory device 205 and attach to the set of press fit holes 1202.
1.3 Set of Alignment Pins Embodiment
In an embodiment, a set of alignment pins are disposed on the configurable CPU package substrate instead of a set of press fit holes. Accordingly, the set of alignment pins may be the removable memory mechanical interface, according to an embodiment of the invention.
In the embodiment illustrated in
Because the flexible substrate 1316 has a U-shaped profile, the flexible substrate 1316 may thus have three different portions. For instance, the flexible substrate 1316 may have an upper portion 1315 and a lower portion 1317 connected together by a bent portion 1319. In an embodiment, the upper portion 1315 is disposed directly above the lower portion 1317. In embodiments, an elastic member 1318 may be disposed between the upper and lower portions 1315 and 1317. The elastic member 1318 may allow a degree of compliance across the upper and lower portions 1315 and 1317 to compensate for uneven contact heights, as will be discussed further herein.
A set of press fit holes 1314 may be disposed in both the upper portion 1315 and lower portion 1317. The press fit holes 1314 may allow the intermediate structure 1308 to align with both the memory device electrical interface 206 and the interconnection structures 1306 during attachment. In an embodiment, alignment is made when the set of alignment pins 1302 inserts through the press fit holes 1314.
An array of top interconnects 1310 may be disposed on the upper portion 1315 of the flexible substrate 1316. In an embodiment, the array of top interconnects 1310 are disposed on a top surface 1320 of the upper portion 1315 as illustrated in
In embodiments, utilizing the intermediate structure 1308 enables both the memory device electrical interface 206 and the interconnection structures 1306 to be formed of an array of pads. Thus, the memory device electrical interface 206 and the interconnection structure 1306 may not significantly protrude from the configurable CPU package substrate 200 and the memory device substrate 1340, respectively. Accordingly, the memory device electrical interface 206 and the interconnection structure 1306 may better resist damage.
To attach the alignment pin counterpart 1303, the intermediate structure 1316 may be first placed onto the memory device electrical interface 206, as illustrated in
Thereafter, in
In an embodiment, the elastic member 1318 disposed between the upper and lower portions 1315 and 1317 allows the top and bottom array of interconnects 1310 and 1312 a certain degree of vertical compliance. By allowing a certain degree of vertical compliance, the elastic member 1318 helps the top and bottom array of interconnects 1310 and 1312 compensate for any abnormalities in interconnect size. In an embodiment, the elastic member 1318 may be formed of any suitable elastic material. For instance, the elastic member 1318 may be formed of a silicone slab or an array of linear springs. To allow for sufficient vertical compliance, the elastic member 1318 may be formed of a suitable thickness. In an embodiment, the thickness of the elastic member 1318 ranges between 1 to 3 mm. In a particular embodiment, the elastic member 1318 is approximately 2 mm thick.
An optional heat sink (not shown) may be used to apply additional enabling force if desired. For instance, a heat sink may apply downward force upon the alignment pin counterpart 1303 to ensure proper electrical coupling.
In embodiments, the memory device 205 is coupled to the configurable CPU package substrate 200 by the static frictional force created between the set of attachment pins 1302 and the set of press fit holes 1304. Accordingly, pulling the alignment pin counterpart 1303 away from the configurable CPU package substrate 200 with a force greater than the static frictional force may thereby remove the memory device 205 from the set of attachment pins 1302 of the configurable CPU package substrate 200. Alternatively, if a heat sink is present, the heat sink may first be removed before pulling the alignment pin counterpart 1303 away from the set of attachment pins 1302. A new press fit hole counterpart 1303 with a new memory device 205 may then replace the old press fit hole counterpart 1303 with the old memory device 205 and attach to the set of alignment pins 1302.
Although embodiments illustrated utilize the intermediate structure 1316 for attaching a removable memory device 205, embodiments are not limited to such applications. For instance, the intermediate structure 1316 may be used to attach an optical module for I/O purposes. The optical module may benefit from the fine pitched array of top and bottom interconnects 1310 and 1312. For instance, the reduced footprint of the fine pitched array may allow additional optical modules to couple to the configurable CPU package substrate 200, thereby increasing device performance.
1.4 Spring-Loaded Clip Embodiment
In an embodiment, the removable memory mechanical interface may be formed of a spring-loaded clip as illustrated in
With brief reference to
To attach the spring-loaded clip counterpart 1403, a downward force 1418 is initially applied to a non-engaging portion 1419 of the top plate 1404, as illustrated in
Once the engaging portion 1421 is lifted, the spring-loaded clip counterpart 1403 may be inserted between the engaging portion 1421 of the top plate 1404 and the configurable CPU package substrate 200, as shown in
After the counterpart 1403 makes contact with the stopping protrusion 1422, the downward force may be released 1420, thereby allowing the spring 1406 to generate a downward clipping force 1428. The clipping force 1428 may draw the engaging portion 1421 of the top plate 1404 toward the configurable CPU package substrate 200. In embodiments, the top plate 1404 may include a locking protrusion 1426 at the end of the engaging portion 1421. The locking protrusion 1426 may fit into the notch 1408 formed in the memory device substrate 1440. If the interconnecting structures 1412 are misaligned with the memory device electrical interface 206, the locking protrusion 1426 may not insert into the notches 1408. Accordingly, the position of the counterpart 1403 may be adjusted until the locking protrusion 1426 fits into the notch 1408. In an embodiment, the top plate 1404 has two locking protrusions 1426, each corresponding to a respective notch illustrated in
Once the counterpart 1403 is attached, as shown in
Once closed, the memory device substrate 1440 may protrude the distance 1415 away from the clip 1402. This protrusion allows a user to grab the substrate 1440 during attachment and removal of the counterpart 1403.
In embodiments, the memory device 205 is coupled to the configurable CPU package substrate 200 by the downward force generated by the spring 1406. Accordingly, applying a downward force onto the non-engaging region 1419 of the top plate 1404 may thereby open the clip 1402 and allow the memory device 205 to be removed from the spring-loaded clip 1402 of the configurable CPU package substrate 200. A new spring-loaded clip counterpart 1403 with a new memory device 205 may then replace the old spring-loaded clip counterpart 1403 with the old memory device 205 and be attached to the spring-loaded clip 1402.
It is to be appreciated that the different embodiments for the removable memory mechanical interface disclosed herein commonly enable a memory device to be removed from a CPU package substrate even after attachment. Removing the memory device may not require a separate tool. Accordingly, any user, such as a customer, may remove and/or replace memory devices on a configurable CPU package substrate according to design requirements.
2.0 Computing System
Depending on its applications, computing device 1500 may include other components that may or may not be physically and electrically coupled to the board 1502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 1506 enables wireless communications for the transfer of data to and from the computing device 1500. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1500 may include a plurality of communication chips 1506. For instance, a first communication chip 1506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 1504 of the computing device 1500 includes an integrated circuit die packaged with a CPU package substrate having removable memory mechanical interfaces, in accordance with implementations of the invention. In some implementations of the invention, the integrated circuit die of the processor includes one or more semiconductor devices. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 1506 also includes an integrated circuit die packaged with a CPU package substrate having removable memory mechanical interfaces, in accordance with implementations of the invention. In accordance with another implementation of the invention, the integrated circuit die of the processor includes one or more semiconductor devices.
In further implementations, another component housed within the computing device 1500 may contain CPU package substrates having removable memory mechanical interfaces in accordance with implementations of the invention.
In various implementations, the computing device 1500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1500 may be any other electronic device that processes data.
In an embodiment, a package substrate includes a processing device interface, a memory device electrical interface disposed on the package substrate, and a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface allows a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
The memory device electrical interface may include a land grid array. In an embodiment, the memory device electrical interface includes an array of pins. In an embodiment, the removable memory mechanical interface has electrical contacts that are in contact with the memory device electrical interface and has exposed electrical contacts for electrical contact to a mechanical counterpart that is to mate with the removable memory mechanical interface and that is integrated with the memory device.
In an embodiment, the removable memory mechanical interface is a sliding rail socket. The sliding rail socket may include an array of angled pins, sliding grooves on two opposing sides of the socket, and a stopping wall. The angled pins may be slanted toward the stopping wall.
In an embodiment, the removable memory mechanical interface is a multi-edge connector socket. The multi-edge connector socket may be a double edge socket including a first portion and a second portion connected at a joint, the first portion extending in a direction at an offset angle from the second portion, an opening extending through the joint and along both the first and second portions, and an array of contacts extending in a direction at an angle half of the offset angle from one of the first and second portion. The first and second portions may have a beveled corner that extends in a direction parallel to the array of contacts. The multi-edge connector socket may be a full edge pin grid array socket that includes a structure body in the shape of a frame, and a plurality of openings in a top surface of the structure body.
In an embodiment, the removable memory mechanical interface includes a housing structure, an array of openings in the housing structure, and an array of pins. Each pin of the array of pins may be disposed in each opening in the array of openings. Each pin may have a curved contacting end. In an embodiment, a first distance from the tip of the curved contacting end to the equator of the curved contacting end is less than a second distance from the tip of an interconnecting solder ball to the equator of the interconnecting solder ball. Each opening of the array of openings may include an interconnection region and a pin deflection region of the solder ball region, the pin deflection region extending from the solder ball region.
In an embodiment, the removable memory mechanical interface is coupled to a counterpart comprised of a strip of flex cable having two opposing ends and a memory device located at one of the opposing ends. The flex cable may have a connection portion at one of the opposing ends, the connection portion mated with the memory device electrical interface. The flex cable may have a second memory device at the other of the opposing ends and a connection portion between the memory devices, the connection portion mated with the memory device electrical interface. The memory device may be attached to a heat sink of a processing device that is connected to the processing device interface.
In an embodiment, the removable mechanical interface includes a pair of sockets with openings disposed horizontally within each socket of the pair of sockets, the memory device to fit horizontally between the pair of sockets. The pair of sockets may have a height that permits the pair of sockets and the memory device to reside beneath a heat sink of a processing device that is connected to the processing device interface.
In an embodiment, the removable memory mechanical interface is a frame socket that comprises an alignment frame and a land grid array, the alignment frame having a notch within one side. The frame socket may be to support reflowable removal of the memory device from the package substrate. In an embodiment, the removable memory mechanical interface includes a set of alignment holes. In an embodiment, the removable memory mechanical interface includes a set of alignment pins. The removable memory mechanical interface may be a spring-loaded clip.
In an embodiment, a package system includes a package substrate, a processing device coupled to the package substrate, a memory device electrical interface disposed on the package substrate, a removable memory mechanical interface disposed proximate to the memory device electrical interface, and a memory device attached to the memory device electrical interface by the removable memory mechanical interface, the removable memory device mechanical interface to permit the memory device to be easily detachable and re-attachable to the memory device electrical interface. The package system may further include a reflowable grid array disposed between the memory device electrical interface and the memory device. The memory device may be electrically coupled to the processing device on the package substrate.
In an embodiment, a method of fabricating a package system includes attaching a processing device to a package substrate, and attaching a memory device to the package substrate by attaching a memory device substrate to a removable memory mechanical interface disposed on the package substrate around a memory device electrical interface.
The memory device substrate may be attached by inserting the memory device substrate into a socket of the removable memory mechanical interface. In an embodiment, the memory device is attached by sliding the memory device substrate into sliding grooves of the removable memory mechanical interface. In an embodiment, the memory device is attached by pressing the memory device substrate onto a housing structure of the removable memory mechanical interface, the housing structure having an array of openings corresponding to an array of solder balls on the memory device substrate. Each opening of the array of openings may have a pin with a curved contacting end disposed inside it. The solder ball may contact the curved contacting end at a point lower than the equator of the curved contacting end.
In an embodiment, a low insertion force connector includes a housing structure, an array of openings within the housing structure, and a pin within each opening of the array of openings, the pin having a curved contacting end. Each opening of the array of openings may have an extended deflection portion that extends from the opening.
In an embodiment, a multi-edge connector includes a substrate having at least two edges that are joined at one end, the two edges forming a separation angle with respect to one another; a single connection interface continuously extending along at least the two edges; and a plurality of pads on the connection interface, each pad of the plurality of pads extending in a direction at an angle half of the separation angle from one of the at least two edges. The multi-edge connector may further include a beveled edge disposed on a corner of the substrate, the beveled edge extending in a direction parallel to the plurality of pads.
In utilizing the various aspects of this invention, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming CPU package substrates with removable memory mechanical interfaces. Although embodiments of the present invention have been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as particularly graceful implementations of the claimed invention useful for illustrating embodiments of the present invention.
Claims
1. A package substrate, comprising:
- a processing device interface to couple to a processing device;
- a memory device electrical interface disposed on the package substrate;
- a removable memory mechanical interface disposed proximately to the memory device electrical interface, the removable memory mechanical interface to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate and without removing the processing device.
2. The package substrate of claim 1, wherein the memory device electrical interface comprises a land grid array.
3. The package substrate of claim 1, wherein the memory device electrical interface comprises an array of pins.
4. The package substrate of claim 1, wherein the removable memory mechanical interface has electrical contacts that are in contact with the memory device electrical interface and has exposed electrical contacts for electrical contact to a mechanical counterpart that is to mate with the removable memory mechanical interface and that is integrated with the memory device.
5. The package substrate of claim 1, wherein the removable memory mechanical interface is a sliding rail socket.
6. The package substrate of claim 5, wherein the sliding rail socket that comprises an array of angled pins, sliding grooves on two opposing sides of the socket, and a stopping wall.
7. The package substrate of claim 6, wherein the angled pins are slanted toward the stopping wall.
8. The package substrate of claim 1, wherein the removable memory mechanical interface is a multi-edge connector socket.
9. The package substrate of claim 8, wherein the multi-edge connector socket is a double edge socket comprising:
- a first portion and a second portion connected at a joint, the first portion extending in a direction at an offset angle from the second portion;
- an opening extending through the joint and along both the first and second portions; and
- an array of contacts extending in a direction at an angle half of the offset angle from one of the first and second portion.
10. The package substrate of claim 9, wherein the first and second portions have a beveled corner that extends in a direction parallel to the array of contacts.
11. The package substrate of claim 8, wherein the multi-edge connector socket is a full edge pin grid array socket, comprising: a plurality of openings in a top surface of the structure body.
- a structure body in the shape of a frame; and
12. The package substrate of claim 1, wherein the removable memory mechanical interface comprises a housing structure, an array of openings in the housing structure, and an array of pins.
13. The package substrate of claim 12, wherein each pin of the array of pins is disposed in each opening in the array of openings.
14. The package substrate of claim 13, wherein each pin has a curved contacting end.
15. The package substrate of claim 14, wherein a first distance from the tip of the curved contacting end to the equator of the curved contacting end is less than a second distance from the tip of an interconnecting solder ball to the equator of the interconnecting solder ball.
16. The package substrate of claim 12, wherein each opening of the array of openings comprises an interconnection region and a pin deflection region of the solder ball region, the pin deflection region extending from the solder ball region.
17. The package substrate of claim 1, wherein the removable memory mechanical interface is coupled to a counterpart comprised of a strip of flex cable having two opposing ends and a memory device located at one of the opposing ends.
18. The package substrate of claim 17, wherein the flex cable has a connection portion at one of the opposing ends, the connection portion mated with the memory device electrical interface.
19. The package substrate of claim 17, wherein the flex cable has a second memory device at the other of the opposing ends and a connection portion between the memory devices, the connection portion mated with the memory device electrical interface.
20. The package substrate of claim 17, wherein the memory device is attached to a heat sink of a processing device that is connected to the processing device interface.
21. The package substrate of claim 1, wherein the removable mechanical interface comprises a pair of sockets with openings disposed horizontally within each socket of the pair of sockets, the memory device to fit horizontally between the pair of sockets.
22. The package substrate of claim 21, wherein the pair of sockets have a height that permits the pair of sockets and the memory device to reside beneath a heat sink of a processing device that is connected to the processing device interface.
23. The package substrate of claim 1, wherein the removable memory mechanical interface is a frame socket that comprises an alignment frame and a land grid array, the alignment frame having a notch within one side.
24. The package of claim 1, wherein the frame socket is to support reflowable removal of the memory device from the package substrate.
25. The package substrate of claim 1, wherein the removable memory mechanical interface includes a set of alignment holes.
26. The package substrate of claim 1, wherein the removable memory mechanical interface includes a set of alignment pins.
27. The package substrate of claim 1, wherein the removable memory mechanical interface is a spring-loaded clip.
28. A package system, comprising:
- a package substrate;
- a processing device coupled to the package substrate;
- a memory device electrical interface disposed on the package substrate;
- a removable memory mechanical interface disposed proximate to the memory device electrical interface; and
- a memory device attached to the memory device electrical interface by the removable memory mechanical interface, the removable memory device mechanical interface to permit the memory device to be easily detachable and re-attachable to the memory device electrical interface without removing the processing device.
29. The package system of claim 28, further comprising a reflowable grid array disposed between the memory device electrical interface and the memory device.
30. The package system of claim 28, wherein the memory device is electrically coupled to the processing device on the package substrate.
31. A method of fabricating a package system, comprising:
- attaching a processing device to a package substrate; and
- attaching a memory device to the package substrate by attaching a memory device substrate to a removable memory mechanical interface disposed on the package substrate around a memory device electrical interface; and,
- removing the memory device from the package substrate without removing the processing device.
32. The method of claim 31, wherein the memory device substrate is attached by inserting the memory device substrate into a socket of the removable memory mechanical interface.
33. The method of claim 31, wherein the memory device is attached by sliding the memory device substrate into sliding grooves of the removable memory mechanical interface.
34. The method of claim 31, wherein the memory device is attached by pressing the memory device substrate onto a housing structure of the removable memory mechanical interface, the housing structure having an array of openings corresponding to an array of solder balls on the memory device substrate.
35. The method of claim 31, wherein each opening of the array of openings has a pin with a curved contacting end disposed inside it.
36. The method of claim 31, wherein the solder ball contacts the curved contacting end at a point lower than the equator of the curved contacting end.
| 5926367 | July 20, 1999 | Gutierrez et al. |
| 5991161 | November 23, 1999 | Samaras |
| 6031729 | February 29, 2000 | Berkely et al. |
| 6114626 | September 5, 2000 | Barnes et al. |
| 6159031 | December 12, 2000 | Llapitan et al. |
| 6327147 | December 4, 2001 | Llapitan et al. |
| 6492718 | December 10, 2002 | Ohmori |
| 6575766 | June 10, 2003 | Xie et al. |
| 6585534 | July 1, 2003 | Llapitan et al. |
| 6597582 | July 22, 2003 | Baba |
| 6671172 | December 30, 2003 | Carter et al. |
| 6672880 | January 6, 2004 | Xie et al. |
| 6702620 | March 9, 2004 | Lynch et al. |
| 6722908 | April 20, 2004 | Llapitan et al. |
| 6830470 | December 14, 2004 | Lynch et al. |
| 6854979 | February 15, 2005 | Xie et al. |
| 6861743 | March 1, 2005 | Kim |
| 6888722 | May 3, 2005 | Viswanath |
| 6979208 | December 27, 2005 | Xie et al. |
| 7050302 | May 23, 2006 | Llapitan et al. |
| 7200934 | April 10, 2007 | Carter et al. |
| 7278859 | October 9, 2007 | Irvine |
| 7602616 | October 13, 2009 | Zhao |
| 7729121 | June 1, 2010 | Deshpande |
| 7888784 | February 15, 2011 | Gurumurthy et al. |
| 7911790 | March 22, 2011 | Carter et al. |
| 8025531 | September 27, 2011 | Zhang et al. |
| 8188594 | May 29, 2012 | Ganesan et al. |
| 8353101 | January 15, 2013 | Gurumurthy et al. |
| 8508947 | August 13, 2013 | Ganesan et al. |
| 8513792 | August 20, 2013 | Ganesan et al. |
| 9307686 | April 5, 2016 | Takada |
| 9516755 | December 6, 2016 | Lam |
| 20020167081 | November 14, 2002 | Kondo |
| 20030222332 | December 4, 2003 | Tran |
| 20090065931 | March 12, 2009 | Rangaraj et al. |
| 20100326716 | December 30, 2010 | Zhang et al. |
| 20120180312 | July 19, 2012 | Zhang et al. |
| 20120188737 | July 26, 2012 | Pai |
| 20120200993 | August 9, 2012 | Aoki |
| 20120262863 | October 18, 2012 | Johnson |
| 20140092573 | April 3, 2014 | Llapitan |
| 20140106582 | April 17, 2014 | Wig et al. |
| 20140113464 | April 24, 2014 | Tran et al. |
| 20140162475 | June 12, 2014 | Chawla et al. |
| 20140174808 | June 26, 2014 | Zhang et al. |
| 20140175644 | June 26, 2014 | Srinivasan et al. |
| 20140195876 | July 10, 2014 | Nachimuthu et al. |
| 20140217571 | August 7, 2014 | Ganesan et al. |
| 20140217579 | August 7, 2014 | Ganesan et al. |
| 20140273552 | September 18, 2014 | Ganesan et al. |
| 1996335486 | December 1996 | JP |
| 2000208696 | July 2000 | JP |
| 2001043920 | February 2001 | JP |
| 2001127217 | May 2001 | JP |
| 2001177051 | June 2001 | JP |
| 2001189412 | July 2001 | JP |
| 2001305260 | November 2001 | JP |
| 2003123922 | April 2003 | JP |
| 2004123234 | April 2004 | JP |
| 2009081022 | April 2009 | JP |
| 2009193677 | August 2009 | JP |
| 2012195452 | October 2012 | JP |
| 201232931 | August 2012 | TW |
- Notice of Allowance for U.S. Appl. No. 104137705, dated Jul. 20, 2017, 3 pgs.
Type: Grant
Filed: Dec 18, 2014
Date of Patent: Nov 28, 2017
Patent Publication Number: 20160183374
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Mani Prakash (University Place, WA), Thomas T. Holden (Olympia, WA), Jeffory L. Smalley (East Olympia, WA), Ram S. Viswanath (Phoenix, AZ), Bassam N. Coury (Dupont, WA), Dimitrios Ziakas (Hillsboro, OR), Chong J. Zhao (West Linn, OR), Jonathan W. Thibado (Beaverton, OR), Gregorio R. Murtagian (Phoenix, AZ), Kuang C. Liu (Queen Creek, AZ), Rajasekaran Swaminathan (Tempe, AZ), Zhichao Zhang (Chandler, AZ), John M. Lynch (Forest Grove, OR), David J. Llapitan (Tacoma, WA), Sanka Ganesan (Chandler, AZ), Xiang Li (Portland, OR), George Vergis (Portland, OR)
Primary Examiner: Anthony Haughton
Assistant Examiner: Yahya Ahmad
Application Number: 14/575,775
International Classification: H05K 1/18 (20060101); H01L 23/00 (20060101); H01R 12/71 (20110101); H01R 12/79 (20110101);
