Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.

Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

Abstract: A composition for improving the solubility of poorly soluble substances is provided. The composition includes about 40-99.5% by weight of cyclodextrin and/or derivatives thereof; about 0.05-10% by weight of at least one water-soluble polymer; and about 0.05-60% by weight of at least one water-soluble stabilizer.

Abstract: An optical system includes an optical module with a main axis is provided. The optical module includes a fixed portion, a movable portion, a driving mechanism, and a supporting assembly. The movable portion is connected to an optical element and is movable relative to the fixed portion. The driving mechanism drives the movable portion to move relative to the fixed portion. The supporting assembly is connected to the movable portion and the fixed portion. When viewed along a direction that is parallel with the main axis, the fixing portion is a polygonal structure with a first side, a second side, a third side, and a fourth side. The first side is parallel with the third side, the second side is parallel with the fourth side, and the first side is not parallel with the second side.

Abstract: An optical system includes an optical module with a main axis is provided. The optical module includes a fixed portion, a movable portion, and a driving mechanism. The movable portion is connected to an optical element and is movable relative to the fixed portion. The driving mechanism drives the movable portion to move relative to the fixed portion. When viewed along a direction that is parallel with the main axis, the fixed portion is a polygonal structure with a first side, a second side, a third side, and a fourth side. The first side is parallel with the third side, the second side is parallel with the fourth side, and the first side is not parallel with the second side.

Abstract: A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varyies at different heights along the side of the photodiode.

Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.

Abstract: This invention is a coaxial cable and a signal transmission assembly thereof. The coaxial cable includes a conductive cored wire, an insulating tape and a metal foil Mylar film a conductive layer and an outer jacket. The conductive cored wire includes an outer peripheral surface. The insulating tape is wrapped onto the outer peripheral surface of the conductive cored wire in a spiral winding manner or a longitudinal wrapping manner. The metal foil Mylar film is wrapped onto the insulating tape in a spiral winding manner, a longitudinal wrapping manner, and the conductive layer is wrapped onto the metal foil Mylar film. The jacket is wrapped onto the conductive layer. A distance between the conductive core wire and the metal foil Mylar film can be adjust by control the number of wrapping turns of the insulating tape to improve the yield rate of the coaxial cable manufacturing.

Abstract: This disclosure is a transmission line, which comprises an inner conducting core, an insulation layer, a conductive layer and an outer sheath. The insulation layer covers the inner conducting core, the conductive layer covers the insulation layer, and the outer sheath covers the conductive layer. The outer sheath at one end or both ends of the transmission line includes a thinned part, wherein the cross-sectional area of the thinned part is smaller than that of the outer sheath. The conductive layer is folded to the thinned part of the outer sheath, and forms a folded part on the thinned part to reduce the cross-sectional area of one end or both ends of the transmission line. A connector is connected to the transmission line without reducing the wire diameter of the inner conducting core, so as to increase the signal transmission distance of the transmission line.

Abstract: This disclosure is a connection mechanism of transmission lines, which comprises two transmission lines, a circuit board, a chip, a metal shell and an insulation shell. The outer sheath at one end of the two transmission lines is removed, and then conducting wires and conductive layers will be exposed. The conducting wires of the two signal transmission lines are connected to each other through the circuit board and the chip, and the metal shell covers the circuit board and the chip. Further, the metal shell is connected to the exposed conductive layer of the two transmission lines, and the insulation shell covers the metal shell and part of the two transmission lines. The connection mechanism is formed between the two transmission lines to extend the length of the transmission line, which improves the connection strength and compensates the attenuation of the transmission signal.

Abstract: A trolley configured for use to carry folding tables of a variety of sizes. The trolley includes a loading end, a trolley frame, and an extension gate adjustably connected to the trolley frame so as to be adjustable relative to the loading end of the trolley in a length direction of the trolley. The extension gate includes an elongate member slidingly disposed on the trolley frame and a rotatable portion that is foldable relative to the elongate member and lockable in an upright position by a lock. The rotatable portion may be positioned in an extended position from the loading end of the trolley, in a retracted position adjacent the loading end of the trolley, and in positions that are intermediate to the extended position and the retracted position. The elongate member may slide in a first direction to extend the rotatable portion away from the loading end of the trolley and in a second direction to retract the rotatable portion toward the loading end of the trolley.

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Abstract: A thunderbolt device module is provided. The thunderbolt device module of the invention includes a first interface protocol component, a thunderbolt controller and a second interface protocol component. A root complex of an electronic device is via a bus, conforming to a PCIe interface protocol, directly or indirectly electrically coupled to the second interface protocol component. The first interface protocol component and the second interface protocol component both conform to a predetermined interface protocol. In particular, the predetermined interface protocol is not the PCIe interface protocol, but supports the PCIe interface protocol. The thunderbolt controller is electrically coupled to the first interface protocol component. The second interface protocol component is electrically coupled to the first interface protocol component. The communication between the second interface protocol component and the first interface protocol component conforms to the predetermined interface protocol.

Abstract: A method of forming a capacitor is disclosed. The method includes forming a portion of a metallization layer on a substrate, forming a via layer on the substrate, and forming a first electrode between the metallization layer and the via layer, where the first electrode is electrically connected to the metallization layer. The method also includes forming a second electrode between the metallization layer and the via layer, where the second electrode is electrically connected to the via layer, and forming a dielectric layer between the first electrode and the second electrode, where the first electrode is not electrically connected to any other conductors other than through the metallization layer, and where the second electrode is not electrically connected to any conductors other than through the via layer.

Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

Abstract: The disclosure provides a method and a host for adjusting audio of speakers, and a computer readable medium. The method includes: controlling a far-field speaker to play a first audio signal; controlling an audio receiver to receive the first audio signal from the far-field speaker and accordingly positioning a speaker location of the far-field speaker; establishing a first hearing transfer function related to the far-filed speaker based on the speaker location of the far-filed speaker; controlling the far-field speaker to play a second audio signal based on a second hearing transfer function; controlling the audio receiver to receive the second audio signal and accordingly estimating a first reference hearing volume; obtaining a second reference hearing volume corresponding to a first near-field speaker; and adjusting a first volume of the far-field speaker based on the first reference hearing volume and the second reference hearing volume.

Abstract: A video residual decoding apparatus includes a residual decoding circuit and a neighbor storage device. The residual decoding circuit applies residual decoding to a transform block, wherein the transform block is divided into M sub-blocks, M is a positive integer, and the M sub-blocks are processed by the residual decoding in a diagonal scan order. The neighbor storage device stores neighbor data that belong to neighboring sub-blocks and are referenced by the residual decoding of a current sub-block, wherein neighbor data belonging to a sub-block is derived from a residual decoding result of the sub-block, and a storage size of the neighbor storage device is not larger than a maximum data amount of neighbor data derived from residual decoding results of N sub-blocks, where N is a positive integer, and N is smaller than M.

Abstract: Actual physical locations of dies on a substrate package may be identified without using a full metrology scan of the substrate. Instead, one or more cameras may be used to efficiently locate the approximate location of any of the alignment features based on their expected positioning in the design file for the packages are substrate. The cameras may then be moved to locations where alignment features should be, and images may be captured to determine the actual location of the alignment feature. These actual locations of the alignment features may then be used to identify coordinates for the dies, as well as rotations and/or varying heights of the dies on the packages. A difference between the expected location from the design file and the actual physical location may be used to adjust instructions for the digital lithography system to compensate for the misalignment of the dies.

Abstract: A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.