Abstract: Disclosed are a semiconductor memory device and a method of programming the same. The semiconductor memory device comprises a plurality of memory cells, each of the memory cells having a plurality of phase change variable resistors and a selection transistor. Each of the phase change variable resistors has a first end connected to one of a plurality of bit lines and a second end connected to a drain of the selection transistor. The selection transistor has a gate connected to a word line and a source connected to a reference voltage. The memory device is programmed by activating a word line associated with a selected memory cell, thereby turning on the selection transistor, applying a reset pulse to bit lines of the selected memory cell, and applying a set pulse to selected bit lines of the selected memory cell.

Abstract: A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

Abstract: A flip chip interface circuit for combining two identical semiconductor chips on upper and lower surfaces of an assembling lead frame into one flip chip package includes at least first and second address pads and first and second bonding option pads formed symmetrically on the chips in a mirror type arrangement to each other. The first and second address pads are input with a signal for selecting operations of the first and second semiconductor chips. The first and second input pad selection and chip selection signals are output in response to signals from the first and second address pads and first and second bonding option pads of the chips, the first and second semiconductor chip selection signals are output in response to the first and second input pad and chip selection signals, and an interface enable signal is output in response to the first and second semiconductor chip selection signals.

Abstract: Phase-change memory devices are provided that include a plurality of phase-change memory cells and a reset pulse generation circuit configured to output a plurality of sequential reset pulses. Each sequential reset pulse is output to a corresponding one of a plurality of reset lines. A plurality of write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. Methods of programming phase-change memory devices using sequential reset control signals are also provided.

Abstract: A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

Abstract: A write driver circuit including a plurality of programmable fuses for a phase change memory device in which a write operation is correctly performed even in the case where a current output shift in a write current generation circuit; or in the case where a phase change memory cell having a phase change property shift due to an external factor or due a process change. The write driver circuit includes a write current control unit for outputting a first or second level of voltage selected, by selecting one of a first or second programmable current path, based on whether a first or second selection pulse signal is applied; and a current driving unit for generating a write current controlled by the output voltage of the write current control unit.

Abstract: A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

Abstract: A write driver circuit including a plurality of programmable fuses for a phase change memory device in which a write operation is correctly performed even in the case where a current output shift in a write current generation circuit; or in the case where a phase change memory cell has a phase change property shift due to an external factor or due a process change. The write driver circuit includes; a write current control unit for outputting a first or second level of voltage selected, by selecting one of a first or second programmable current path, based on whether a first or second selection pulse signal is applied; and a current driving unit for generating a write current controlled by the output voltage of the write current control unit.

Abstract: Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a reset state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

Abstract: A firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation are described. The phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block.

Abstract: In the method of programming a phase change memory cell, having a lower resistive state and a higher resistive state, to the lower resistive state, the memory cell is heated to first temperature. Subsequently, the memory cell is heated to second temperature, which is greater than the first temperature.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: A writing driver circuit of a phase-change memory array comprising a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

Abstract: A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.

Abstract: A flip chip interface circuit for combining two identical semiconductor chips on upper and lower surfaces of an assembling lead frame into one flip chip package includes at least first and second address pads and first and second bonding option pads formed symmetrically on the chips in a mirror type arrangement to each other. The first and second address pads are input with a signal for selecting operations of the first and second semiconductor chips. The first and second input pad selection and chip selection signals are output in response to signals from the first and second address pads and first and second bonding option pads of the chips, the first and second semiconductor chip selection signals are output in response to the first and second input pad and chip selection signals, and an interface enable signal is output in response to the first and second semiconductor chip selection signals.

Abstract: The invention discloses a semiconductor memory device in which faulty cells causing standby current failure will be replaced with redundancy cells. The semiconductor memory device includes: a plurality of word lines, a plurality of bit lines, a plurality of cells connected between the word lines and bit lines for storing data and a memory cell array of a plurality of cell blocks having a plurality of cell power lines for providing supply voltage to the cells; a plurality of row decoder circuits for decoding external row addresses and generating selection signals for predetermined word lines included in the cell blocks; and a plurality of cell power repairing circuits for selectively blocking between cell power lines providing supply voltage to faulty cells and power source at an occurrence of faulty cells causing standby current failure.

Abstract: A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.