Abstract: Apparatuses, systems, and methods for address based memory performance. A memory array may include a first performance region and a second performance region, each of which may have different performance characteristics from each other. The second region may be distinguished from the first region based on the addresses which are associated with each region. The second performance region may have different performance characteristics based on differences in the layout, components, logic circuits, and combinations thereof. For example, the second region, compared to the first region, may have reduced difference to the data terminals, reduced length of digit lines, a different type of sense amplifier, different refresh address tracking, and combinations thereof. The controller may perform access operations on the memory with different timing based on which region of the memory is accessed.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Apparatuses, systems and methods for dynamic timing of row pull-down operations are described herein. When a word line is accessed, the row decoder may drive that word line to an active voltage, and then to an intermediate voltage. The row decoder may maintain that word line at the intermediate voltage until another word line in the same group of word lines as the accessed word line receives an access command, at which point the first word line is driven to an inactive voltage. For example, if the word lines are grouped by bank, then after an access to a first word line, the first word line may be maintained at the intermediate voltage until a second wordline in the same bank as the first word line is accessed. This may help to mitigate the effect on other nearby word lines of driving a word line to the inactive voltage.

Abstract: Examples described include precharge operations and circuitry for performing precharge operations. Digit lines may be driven to ground during a portion of example precharge operations. By driving the digit lines to ground, charge accumulating in bodies of vertical access devices may be discharged to the digit lines in some examples. To drive the digit lines to ground, a dynamic reference may be used where the reference is ground during one portion of the precharge operation and another value, which may be between two supply voltages (e.g. VCC/2), during another portion of the precharge operation.

Abstract: Examples described include precharge operations and circuitry for performing precharge operations. Digit lines may be driven to ground during a portion of example precharge operations. By driving the digit lines to ground, charge accumulating in bodies of vertical access devices may be discharged to the digit lines in some examples. To drive the digit lines to ground, a dynamic reference may be used where the reference is ground during one portion of the precharge operation and another value, which may be between two supply voltages (e.g. VCC/2), during another portion of the precharge operation.