Patents by Inventor Befruz Tasbas
Befruz Tasbas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088151Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: ApplicationFiled: August 9, 2023Publication date: March 14, 2024Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 11735589Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: GrantFiled: July 6, 2022Date of Patent: August 22, 2023Assignee: pSemi CorporationInventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Publication number: 20230065101Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: ApplicationFiled: July 6, 2022Publication date: March 2, 2023Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Publication number: 20220278027Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.Type: ApplicationFiled: April 26, 2022Publication date: September 1, 2022Applicant: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Patent number: 11387235Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: GrantFiled: August 19, 2020Date of Patent: July 12, 2022Assignee: pSemi CorporationInventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 11335627Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.Type: GrantFiled: January 8, 2020Date of Patent: May 17, 2022Assignee: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Publication number: 20210035973Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: ApplicationFiled: August 19, 2020Publication date: February 4, 2021Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 10763257Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: GrantFiled: September 24, 2019Date of Patent: September 1, 2020Assignee: pSemi CorporationInventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Publication number: 20200144163Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.Type: ApplicationFiled: January 8, 2020Publication date: May 7, 2020Applicant: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Publication number: 20200091148Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: ApplicationFiled: September 24, 2019Publication date: March 19, 2020Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 10546804Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.Type: GrantFiled: September 20, 2018Date of Patent: January 28, 2020Assignee: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Patent number: 10446687Abstract: A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the leadframe, and a top semiconductor die. The bottom semiconductor die has a first frontside active layer with first frontside electrical contacts electrically connected to the leadframe, a first backside portion, and a buried oxide layer situated between the first frontside active layer and the first backside portion. The top semiconductor die is mounted to the first backside portion. The first frontside active layer includes a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer. The first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead through a first electrical contact of the first frontside electrical contacts to minimize crosstalk.Type: GrantFiled: January 18, 2019Date of Patent: October 15, 2019Assignee: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Patent number: 10438950Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: GrantFiled: April 14, 2017Date of Patent: October 8, 2019Assignee: pSemi CorporationInventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 10424666Abstract: A semiconductor package includes a leadframe having perimeter package leads and electrical connectors, a single semiconductor die having a back-side electrical contact and front-side electrical contacts, an electrically conductive clip (“clip”), and a top semiconductor die having a frontside and a backside. The single semiconductor die includes two or more transistors. Two or more of the front-side electrical contacts of the semiconductor die are electrically coupled to and physically mounted to respective electrical contacts of the leadframe. An electrical contact surface of the clip is electrically coupled to and physically mounted to an electrical connector of the leadframe. Another electrical contact surface of the clip is physically mounted to and electrically coupled to the back-side electrical contact of the semiconductor die. The backside of the top semiconductor die is physically mounted to yet another surface of the electrically conductive clip.Type: GrantFiled: August 17, 2017Date of Patent: September 24, 2019Assignee: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Publication number: 20190157446Abstract: A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the leadframe, and a top semiconductor die. The bottom semiconductor die has a first frontside active layer with first frontside electrical contacts electrically connected to the leadframe, a first backside portion, and a buried oxide layer situated between the first frontside active layer and the first backside portion. The top semiconductor die is mounted to the first backside portion. The first frontside active layer includes a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer. The first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead through a first electrical contact of the first frontside electrical contacts to minimize crosstalk.Type: ApplicationFiled: January 18, 2019Publication date: May 23, 2019Applicant: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Patent number: 10249759Abstract: In an active layer over a semiconductor substrate, a semiconductor device has a first lateral diffusion field effect transistor (LDFET) that includes a source, a drain, and a gate, and a second LDFET that includes a source, a drain, and a gate. The source of the first LDFET and the drain of the second LDFET are electrically connected to a common node. A first front-side contact and a second front-side contact are formed over the active layer, and a substrate contact electrically connected to the semiconductor substrate is formed. Each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.Type: GrantFiled: February 20, 2018Date of Patent: April 2, 2019Assignee: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Patent number: 10192989Abstract: A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the leadframe, and a top semiconductor die. The bottom semiconductor die has a first frontside active layer with first frontside electrical contacts electrically connected to the leadframe, a first backside portion, and a buried oxide layer situated between the first frontside active layer and the first backside portion. The top semiconductor die is mounted to the first backside portion. The first frontside active layer includes a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer. The first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead through a first electrical contact of the first frontside electrical contacts to minimize crosstalk.Type: GrantFiled: December 22, 2017Date of Patent: January 29, 2019Assignee: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Publication number: 20190027428Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.Type: ApplicationFiled: September 20, 2018Publication date: January 24, 2019Applicant: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Patent number: 10083897Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.Type: GrantFiled: June 30, 2017Date of Patent: September 25, 2018Assignee: SILANNA ASIA PTE LTDInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
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Publication number: 20180240737Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.Type: ApplicationFiled: June 30, 2017Publication date: August 23, 2018Applicant: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang