Patents by Inventor Behnam Sedighi
Behnam Sedighi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962317Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.Type: GrantFiled: May 31, 2022Date of Patent: April 16, 2024Assignee: QUALCOMM IncorporatedInventors: Behnam Sedighi, Shi Bu, Elias Dagher, Dinesh Jagannath Alladi
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Publication number: 20240097694Abstract: Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventor: Behnam SEDIGHI
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Publication number: 20240097698Abstract: Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventor: Behnam SEDIGHI
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Publication number: 20240063765Abstract: Techniques and apparatus for reducing sensitivity (e.g., less gain variation due to parasitic capacitance) in dynamic amplifiers. One example dynamic amplifier generally includes a pair of differential input transistors, a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier, a first pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes, and a second pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Inventor: Behnam SEDIGHI
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Patent number: 11901909Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.Type: GrantFiled: May 20, 2022Date of Patent: February 13, 2024Assignee: QUALCOMM IncorporatedInventors: Igor Gutman, Behnam Sedighi, Tao Luo, Elias Dagher, Jeremy Darren Dunworth
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Publication number: 20230387929Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.Type: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: Behnam SEDIGHI, Shi BU, Elias DAGHER, Dinesh Jagannath ALLADI
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Publication number: 20230378970Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Igor GUTMAN, Behnam SEDIGHI, Tao LUO, Elias DAGHER, Jeremy Darren DUNWORTH
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Publication number: 20230370085Abstract: A capacitor device comprises a semiconductor substrate with multiple metal layers above the substrate. a first metal layer has a first plurality of bottom terminals elongated in a first direction, and a first plurality of top terminals, electrically coupled to each other, elongated in the first direction and interleaved with the first plurality of bottom terminals. A second metal layer between the semiconductor substrate and the first metal layer has a second plurality of bottom terminals elongated in the first direction, and a second plurality of top terminals, electrically coupled to each other and the first plurality of top terminals, elongated in the first direction and interleaved with the second plurality of bottom terminals.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Inventors: Lei SUN, Aram AKHAVAN, Behnam SEDIGHI, Tszwing CHOI, Henry LAU
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Patent number: 11705921Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.Type: GrantFiled: June 3, 2021Date of Patent: July 18, 2023Assignee: QUALCOMM IncorporatedInventors: Xilin Liu, Nitz Saputra, Behnam Sedighi, Ashok Swaminathan, Dongwon Seo
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Patent number: 11569801Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.Type: GrantFiled: March 11, 2021Date of Patent: January 31, 2023Assignee: QUALCOMM IncorporatedInventors: Liang Dai, Kentaro Yamamoto, Behnam Sedighi
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Patent number: 11476841Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.Type: GrantFiled: March 11, 2021Date of Patent: October 18, 2022Assignee: QUALCOMM IncorporatedInventors: Liang Dai, Kentaro Yamamoto, Behnam Sedighi
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Publication number: 20220294433Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Liang Dai, Kentaro Yamamoto, Behnam Sedighi
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Publication number: 20210391871Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.Type: ApplicationFiled: June 3, 2021Publication date: December 16, 2021Inventors: Xilin LIU, Nitz SAPUTRA, Behnam SEDIGHI, Ashok SWAMINATHAN, Dongwon SEO
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Patent number: 10797720Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.Type: GrantFiled: March 28, 2019Date of Patent: October 6, 2020Assignee: QUALCOMM IncorporatedInventors: Eunyung Sung, Nitz Saputra, Behnam Sedighi, Ashok Swaminathan, Honghao Ji, Shahin Mehdizad Taleie, Dongwon Seo
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Patent number: 10686476Abstract: An RF-DAC transmitter is provided that includes an in-phase channel, a quadrature-phase channel, a first intermediate-phase channel, and a second intermediate-phase channel. Each channel includes a pair of interleaved RF-DACs for producing a pair of interleaved RF signals and a subtractor.Type: GrantFiled: May 20, 2019Date of Patent: June 16, 2020Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Nitz Saputra, Chen Jiang, Behnam Sedighi, Ibrahim Ramez Chamas, Bhushan Shanti Asuri, Dongwon Seo
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Publication number: 20200169266Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.Type: ApplicationFiled: November 28, 2018Publication date: May 28, 2020Inventors: Shahin MEHDIZAD TALEIE, Behnam SEDIGHI, Dongwon SEO, Parisa MAHMOUDIDARYAN, Bhushan Shanti ASURI, Sang-June PARK, Shrenik PATEL
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Patent number: 10666285Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.Type: GrantFiled: November 28, 2018Date of Patent: May 26, 2020Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Behnam Sedighi, Dongwon Seo, Parisa Mahmoudidaryan, Bhushan Shanti Asuri, Sang-June Park, Shrenik Patel
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Publication number: 20200099389Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.Type: ApplicationFiled: March 28, 2019Publication date: March 26, 2020Inventors: Eunyung Sung, Nitz Saputra, Behnam Sedighi, Ashok Swaminathan, Honghao Ji, Shahin Mehdizad Taleie, Dongwon Seo
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Patent number: 10516412Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.Type: GrantFiled: September 21, 2018Date of Patent: December 24, 2019Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Ashok Swaminathan, Sudharsan Kanagaraj, Negar Rashidi, Siyu Yang, Behnam Sedighi, Honghao Ji, Jaswinder Singh, Andrew Weil, Dongwon Seo, Xilin Liu
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Patent number: 10454487Abstract: The present disclosure describes aspects of segmented resistor architecture for digital-to-analog converters (DACs). In some aspects, a DAC circuit is implemented with a first resistor network coupled to a set of binary code-controlled current sources and a second resistor network that includes a resistor coupled between the first resistor network and an output of the DAC circuit. A set of thermometer code-controlled current sources are coupled to a node of the second resistor network and provide varying amounts of current. This current is scaled based on a resistance of the second resistor network's resistor, which is higher than a resistance of the first resistor network and effective to increase a combined output impedance of the first and second resistor networks. The increase of output impedance reduces noise of the resistor networks that transfers to the output of the DAC circuit, thereby improving signal-to-noise performance of the DAC circuit.Type: GrantFiled: August 30, 2018Date of Patent: October 22, 2019Assignee: QUALCOMM IncorporatedInventors: Behnam Sedighi, Andrew Weil, Nitz Saputra