Patents by Inventor Behnam Sedighi
Behnam Sedighi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10454509Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.Type: GrantFiled: April 25, 2018Date of Patent: October 22, 2019Assignee: QUALCOMM IncorporatedInventors: Bhushan Shanti Asuri, Krishnaswamy Thiagarajan, Ashok Swaminathan, Shahin Mehdizad Taleie, Yen-Wei Chang, Vinod Panikkath, Sameer Vasantlal Vora, Ayush Mittal, Tonmoy Biswas, Sy-Chyuan Hwu, Zhilong Tang, Ibrahim Chamas, Ping Wing Lai, Behnam Sedighi, Dongwon Seo, Nitz Saputra
-
Publication number: 20190288722Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.Type: ApplicationFiled: April 25, 2018Publication date: September 19, 2019Inventors: Bhushan Shanti ASURI, Krishnaswamy THIAGARAJAN, Ashok SWAMINATHAN, Shahin MEHDIZAD TALEIE, Yen-Wei CHANG, Vinod PANIKKATH, Sameer Vasantlal VORA, Ayush MITTAL, Tonmoy BISWAS, Sy-Chyuan HWU, Zhilong TANG, Ibrahim CHAMAS, Ping Wing LAI, Behnam SEDIGHI, Dongwon SEO, Nitz SAPUTRA
-
Patent number: 10305361Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.Type: GrantFiled: September 20, 2017Date of Patent: May 28, 2019Assignee: QUALCOMM IncorporatedInventors: Nitz Saputra, Sang Min Lee, Dongwon Seo, Vinay Kundur, Behnam Sedighi, Honghao Ji
-
Publication number: 20180358883Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.Type: ApplicationFiled: September 20, 2017Publication date: December 13, 2018Inventors: Nitz SAPUTRA, Sang Min LEE, Dongwon SEO, Vinay KUNDUR, Behnam SEDIGHI, Honghao JI
-
Patent number: 9935654Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.Type: GrantFiled: February 6, 2015Date of Patent: April 3, 2018Assignee: Alcatel-Lucent USA Inc.Inventors: Behnam Sedighi, Nagaraj Prasanth Anthapadmanabhan, Dusan Suvakovic
-
Patent number: 9825132Abstract: An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.Type: GrantFiled: October 13, 2015Date of Patent: November 21, 2017Assignee: University of Notre Dame du LacInventors: Behnam Sedighi, Xiaobo Sharon Hu, Michael Niemier, Joseph Nahas
-
Patent number: 9819357Abstract: The present disclosure describes aspects of current removal for digital-to-analog converters (DACs). In some aspects, a circuit for converting a digital input to an analog output includes a first resistor ladder having first resistors connectable to respective current sources and connected to a first output of the circuit. The circuit also includes second resistor ladder having second resistors connectable to the respective current sources and connected to a second output of the circuit. A common node is formed between common resistor terminals of the first resistor ladder and the second resistor ladder. Current removal circuitry is connected to the common node and referenced to an amount of current provided by the respective current sources. By removing current from the common node of the resistor ladders, common-mode current at outputs of the circuit can be reduced with minimal degradation of differential performance of the circuit.Type: GrantFiled: May 11, 2017Date of Patent: November 14, 2017Assignee: QUALCOMM IncorporatedInventors: Wei Guo, Sang Min Lee, Behnam Sedighi, Dongwon Seo
-
Patent number: 9712146Abstract: Various processor architectures for mixed signal computation exploit the unique characteristics of advanced CMOS technologies, such as fin-based, multi-gate field effect transistors, and/or emerging technologies such as tunnel field effect transistors (TFETs). The example processors disclosed herein are cellular neural network (CNN)-inspired and eliminate the need for voltage controlled current sources (VCCSs), which have previously been utilized to realize feedback and feed-forward templates in CNNs and are the dominant source of power consumption in a CNN array. The example processors replace VCCSs with comparators, which can be efficiently realized with TFETs given their high intrinsic gain. Power efficiencies are in the order of 10,000 giga-operations per second per Watt (GOPS/W), which represents an improvement of more than ten times over state-of-the-art architectures seeking to accomplish similar information processing tasks.Type: GrantFiled: September 18, 2015Date of Patent: July 18, 2017Assignee: University of Notre Dame du LacInventors: Behnam Sedighi, Michael Niemier, Xiaobo Sharon Hu, Indranil Palit
-
Publication number: 20170103979Abstract: An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.Type: ApplicationFiled: October 13, 2015Publication date: April 13, 2017Inventors: Behnam Sedighi, Xiaobo Sharon Hu, Michael Niemier, Joseph Nahas
-
Publication number: 20170085255Abstract: Various processor architectures for mixed signal computation exploit the unique characteristics of advanced CMOS technologies, such as fin-based, multi-gate field effect transistors, and/or emerging technologies such as tunnel field effect transistors (TFETs). The example processors disclosed herein are cellular neural network (CNN)-inspired and eliminate the need for voltage controlled current sources (VCCSs), which have previously been utilized to realize feedback and feed-forward templates in CNNs and are the dominant source of power consumption in a CNN array. The example processors replace VCCSs with comparators, which can be efficiently realized with TFETs given their high intrinsic gain. Power efficiencies are in the order of 10,000 giga-operations per second per Watt (GOPS/W), which represents an improvement of more than ten times over state-of-the-art architectures seeking to accomplish similar information processing tasks.Type: ApplicationFiled: September 18, 2015Publication date: March 23, 2017Inventors: Behnam Sedighi, Michael Niemier, Xiaobo Sharon Xu, Indranil Palit
-
Patent number: 9590657Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.Type: GrantFiled: February 6, 2015Date of Patent: March 7, 2017Assignee: Alcatel-Lucent USA Inc.Inventors: Behnam Sedighi, Nagaraj Prasanth Anthapadmanabhan, Dusan Suvakovic
-
Publication number: 20160233883Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.Type: ApplicationFiled: February 6, 2015Publication date: August 11, 2016Applicant: Alcatel-Lucent USA Inc.Inventors: Behnam Sedighi, Nagaraj Prasanth Anthapadmanabhan, Dusan Suvakovic
-
Publication number: 20160233884Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.Type: ApplicationFiled: February 6, 2015Publication date: August 11, 2016Applicant: Alcatel-Lucent USA Inc.Inventors: Behnam Sedighi, Nagaraj Prasanth Anthapadmanabhan, Dusan Suvakovic
-
Publication number: 20160182055Abstract: A Boolean gate includes at least one symmetric tunneling field-effect transistor (SymFET) for low-power information processing. SymFETs are ideal for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits. Negative differential resistance (NDR) behavior of SymFETs leads to hysteresis in inverters and buffers, and can be used to build simple Schmitt-triggers. Further, pseudo-SymFET loads may be utilized in circuits similar to all-n-type or dynamic logic. For example, latches and flip-flops as well as NAND, NOR, IMPLY, and MAJORITY gates may employ SymFETs. Such SymFET-based devices require fewer transistors than static CMOS-based designs.Type: ApplicationFiled: December 22, 2014Publication date: June 23, 2016Applicant: University of Notre Dame du LacInventors: Behnam Sedighi, Michael Niemier, X. Sharon Hu, Joseph J. Nahas
-
Patent number: 9362919Abstract: A Boolean gate includes at least one symmetric tunneling field-effect transistor (SymFET) for low-power information processing. SymFETs are ideal for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits. Negative differential resistance (NDR) behavior of SymFETs leads to hysteresis in inverters and buffers, and can be used to build simple Schmitt-triggers. Further, pseudo-SymFET loads may be utilized in circuits similar to all-n-type or dynamic logic. For example, latches and flip-flops as well as NAND, NOR, IMPLY, and MAJORITY gates may employ SymFETs. Such SymFET-based devices require fewer transistors than static CMOS-based designs.Type: GrantFiled: December 22, 2014Date of Patent: June 7, 2016Assignee: University of Notre Dame du LacInventors: Behnam Sedighi, Michael Niemier, X. Sharon Hu, Joseph J. Nahas
-
Publication number: 20130089330Abstract: A method and apparatus for providing an efficient optical access network. In a preferred embodiment, a single light source is used to generate light in a network node, such as an OLT (optical line terminal). The generated light is then distributed using an optical splitter to a plurality of outputs, each associated with an ONU. The distributed light intended for a particular ONU (optical network unit) is modulated, for example by an EOM (electro-optical modulator), with a signal carrying communications for the intended ONU. The OLT includes a bank of EOMs or other kind of optical modulators, such as EAMs for serving a plurality of ONUs. The OLT may also include a second light source for generating light that is propagated to one or more of the ONUs for their use in forming upstream transmissions.Type: ApplicationFiled: June 22, 2012Publication date: April 11, 2013Applicant: Alcatel-Lucent USA Inc.Inventors: Hungkei Keith Chow, Peter J. Vetter, Ka-Lun Lee, Behnam Sedighi, Rodney Tucker