Abstract: Disclosed herein are related to a device and a method for sensing a temperature. In one aspect, the device includes a first resistor including a first metal rail in a first layer. The first metal rail may have a first thermal-resistance coefficient. In one aspect, the device includes a second resistor including a second metal rail in a second layer above the first layer along a direction. The second metal rail may have a second thermal-resistance coefficient. In one aspect, the device includes a sensing circuit coupled to the first resistor and the second resistor. The sensing circuit may be configured to determine a temperature, according to the first metal rail having the first thermal-resistance coefficient and the second metal rail having the second thermal-resistance coefficient.

Abstract: A temperature sensor circuit, a control circuit, and a control method are provided. The temperature sensor circuit comprises a temperature sensor and a control circuit. The control circuit is coupled to the temperature sensor and comprises a current source, a sampling circuit, and a computing circuit. The current source is configured to provide a first current and a second current to the temperature sensor in different time periods. The sampling circuit is coupled to the temperature sensor and configured to obtain and store a first voltage information and a second voltage information from the temperature sensor when the first current and second current are respectively provided. The computing circuit is coupled to the sampling circuit and configured to generate a sensing result corresponding to a difference of subtracting the second voltage information from the first voltage information.

Abstract: A method of operating a circuit includes providing the circuit, the circuit includes an operational amplifier, a plurality of sampling switches, a plurality of holding switches, and a plurality of combined switches. The method further includes: during a first phase, causing the plurality of sampling switches to be closed, the plurality of the holding switches to be open, and the plurality of combined switches to be open; during a second phase, causing the plurality of combined switches to be closed; during a third phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be open; and during a fourth phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be closed.

Abstract: A noise detecting circuit including an amplifier circuit amplifying an input signal indicating a noise level of a circuit to be detected and output an amplified signal; a filtering circuit receiving and filtering the amplified signal and output a filtered signal; and a comparing circuit receiving and compare the filtered signal to a reference voltage and output an output signal; wherein the filtering circuit includes: an output terminal; and a first filter selectively coupled to the output terminal, including: a sub-output terminal; a switch selectively coupling the sub-output terminal to the output terminal; a resistor, wherein a terminal of the resistor is coupled to the amplifier circuit and another terminal of the resistor is coupled to the sub-output terminal; and a capacitor, wherein a terminal of the capacitor is coupled to the sub-output terminal and another terminal of the capacitor is coupled to a reference voltage source.

Abstract: A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.

Abstract: A circuit includes an operational amplifier, a plurality of input capacitors, a plurality of output capacitors, a plurality of sampling switches, a plurality of holding switches, a plurality of combined switches. The input capacitors include a first input capacitor and a second input capacitor. The output capacitors include a first output capacitor and a second output capacitor. The sampling switches include a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch. The holding switches include a first holding switch and a second holding switch. The combined switches include a first combined switch and a second combined switch.

Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

Abstract: A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.

Abstract: A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.

Abstract: A circuit includes an operational amplifier, a plurality of input capacitors, a plurality of output capacitors, a plurality of sampling switches, a plurality of holding switches, a plurality of combined switches. The input capacitors include a first input capacitor and a second input capacitor. The output capacitors include a first output capacitor and a second output capacitor. The sampling switches include a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch. The holding switches include a first holding switch and a second holding switch. The combined switches include a first combined switch and a second combined switch.

Abstract: A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.

Abstract: A continuous time delta sigma modulator is described in this application. In one example, the continuous time delta sigma modulator includes: a quantizer, a buffer module, a randomizer, and a reference module. The quantizer includes a comparator that generates a digital output based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module stores the digital output for a predetermined delay period and outputs the digital output after the predetermined delay period as a delayed digital output. The randomizer randomizes the delayed digital output to generate a randomized digital output. The reference module modifies the reference potential based on the randomized digital output.

Abstract: A continuous time delta sigma modulator is disclosed. In one example, the continuous time delta sigma modulator includes: a quantizer, a buffer module, a randomizer, and a reference module. The quantizer includes a comparator that generates a digital output based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module stores the digital output for a predetermined delay period and outputs the digital output after the predetermined delay period as a delayed digital output. The randomizer randomizes the delayed digital output to generate a randomized digital output. The reference module modifies the reference potential based on the randomized digital output.

Abstract: A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures, an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures, and a dummy buffer zone surrounding the PMOS and NMOS arrays. The semiconductor structure has a uniform spacing between OD structures in the first and second sets of OD structures and between the PMOS and NMOS array, such that no dummy buffer zone is included between the PMOS array and the NMOS array.

Abstract: A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures, an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures, and a dummy buffer zone surrounding the PMOS and NMOS arrays. The semiconductor structure has a uniform spacing between OD structures in the first and second sets of OD structures and between the PMOS and NMOS array, such that no dummy buffer zone is included between the PMOS array and the NMOS array.