Patents by Inventor Ben Rogel-Favila

Ben Rogel-Favila has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150355271
    Abstract: In an embodiment, a testing system includes a frame, a DUT (device under test) testing module. The frame has at least one aperture extending from a front side of the frame to a rear side of the frame. The DUT testing module is inserted into the at least one aperture. The DUT testing module is operable to receive and hold a DUT receptacle including an electrical interface, an air flow interface, and a DUT coupled to the electrical interface. The DUT receptacle is configured to enclose and hold inside the DUT. Further, the DUT testing module is operable to couple to and to use the electrical interface and the air flow interface to perform a test at a controlled temperature on the DUT that is inside of the DUT receptacle.
    Type: Application
    Filed: June 10, 2015
    Publication date: December 10, 2015
    Inventors: Ben ROGEL-FAVILA, James FISHMAN
  • Publication number: 20150355231
    Abstract: In an embodiment, a universal test cell includes a plurality of test slots configured to receive a plurality of universal test containers each including similar dimensions. Each universal test container is configured to enclose each of a plurality of different devices to test. Each universal test container includes an external electrical interface configured to couple to each of the plurality of different devices to test. The universal test cell is configured to test the plurality of different devices while each is located within a universal test container of the plurality of universal test containers. The universal test cell includes a plurality of universal electrical interfaces that are each configured to couple with the external electrical interface of each universal test container.
    Type: Application
    Filed: October 15, 2014
    Publication date: December 10, 2015
    Inventors: Ben ROGEL-FAVILA, Roland WOLFF, Eric KUSHNICK, James FISHMAN
  • Publication number: 20150355279
    Abstract: In an embodiment, a method includes causing a test floor system to insert a DUT (device under test) into a DUT receptacle. This is performed in a manner that couples the DUT to an electrical interface of the DUT receptacle and that encloses the DUT inside the DUT receptacle to facilitate testing of the DUT. Also, the method includes causing the test floor system to transport the DUT receptacle that encloses the DUT to a tester of the test floor system and to insert the DUT receptacle into a DUT testing module of the tester. Further, the method includes causing the test floor system to determine identification information of the DUT. Furthermore, the method includes, based on the identification information, sending a test routine to the DUT testing module to perform on the DUT.
    Type: Application
    Filed: June 10, 2015
    Publication date: December 10, 2015
    Inventors: Ben ROGEL-FAVILA, Padmaja NALLURI, Kirsten ALLISON
  • Publication number: 20150355230
    Abstract: In one embodiment, a universal test container can include a universal external electrical interface configured to couple to each of a plurality of different devices to test. In addition, the universal test container is configured to enclose each of the plurality of different devices to test.
    Type: Application
    Filed: October 15, 2014
    Publication date: December 10, 2015
    Inventors: Ben ROGEL-FAVILA, Roland WOLFF, Eric KUSHNICK, James FISHMAN
  • Publication number: 20150355268
    Abstract: In an embodiment, a test floor apparatus includes at least one conveyor, a vertical stack buffer, and an automated handling station. The vertical stack buffer is operable to hold a plurality of DUT (device under test) receptacles and operable to place a DUT receptacle on the at least one conveyor to enable a corresponding DUT to be inserted into the DUT receptacle. The automated handling station is operable to access the DUT receptacle from the at least one conveyor and is operable to open the DUT receptacle to position the corresponding DUT in a manner that couples the corresponding DUT to an electrical interface of the DUT receptacle and that encloses the corresponding DUT inside the DUT receptacle to facilitate testing of the corresponding DUT.
    Type: Application
    Filed: June 10, 2015
    Publication date: December 10, 2015
    Inventors: Ben ROGEL-FAVILA, James FISHMAN
  • Publication number: 20150355229
    Abstract: In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers.
    Type: Application
    Filed: October 15, 2014
    Publication date: December 10, 2015
    Inventors: Ben ROGEL-FAVILA, Roland WOLFF, Eric KUSHNICK, James FISHMAN, Mei-Mei SU
  • Publication number: 20150355270
    Abstract: In an embodiment, a testing apparatus includes an air mixing chamber, a docking unit, and a DUT (device under test) test execution unit. The air mixing chamber includes a first air inlet operable to receive a first air flow, a second air inlet operable to receive a second air flow, and an air outlet operable to output a mixed air flow. The docking unit is operable to receive and to securely hold a DUT (device under test) receptacle including an electrical interface, an air flow interface, and a DUT coupled to the electrical interface. The DUT receptacle is configured to enclose and hold inside the DUT. The docking unit is operable to couple to the electrical interface and to the air flow interface. The docking unit is operable to receive and to send the mixed air flow to the DUT receptacle. A DUT test execution unit is coupled to the docking unit. The DUT test execution unit is operable to perform a test on the DUT that is inside of the DUT receptacle.
    Type: Application
    Filed: June 10, 2015
    Publication date: December 10, 2015
    Inventors: Ben ROGEL-FAVILA, James FISHMAN
  • Patent number: 7853828
    Abstract: A hardware independent and graphically extensible tester state browsing technique for observing and modifying operating state of test equipment includes accessing a descriptor file describing an architecture of the test equipment, invoking a set of plugins associated with one or more subsystems of the test equipment, and displaying a map with a set of drill-down mechanisms each associated with different ones of the subsystems of the test equipment which invoke the respective plugin associated with its corresponding respective subsystem.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: December 14, 2010
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Jeffrey Johnson, Ben Rogel-Favila, Alan Davis
  • Patent number: 7711524
    Abstract: A method and system generate a boundary of a Schmoo plot. In accord with the method, a plurality of seed points having a resolution that is less than or equal to ½ the acquisition resolution indicated by a smoothness of a representative Schmoo boundary are selected. A coarse boundary search is performed to identify a plurality of test points that are within an acquisition resolution of the boundary. The test points that comprise the coarse boundary are interpolated to produce a fine estimate of the boundary.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: May 4, 2010
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Lokesh Johri, Kaushik Ghosh, Ben Rogel-Favila
  • Publication number: 20070260932
    Abstract: The present invention is an event log management system and method for monitoring the reliability of test systems. An event log management system includes a data store which stores at least one tester configuration file, a hardware independent event capture function which captures events from at least one monitored tester associated with one of the at least one test configuration files, a graphical user interface which receives issue information from a user, and a server which manages storage and tracking of the captured events.
    Type: Application
    Filed: April 11, 2006
    Publication date: November 8, 2007
    Inventors: Ryan Prichard, Ben Rogel-Favila
  • Publication number: 20070156352
    Abstract: A method and system generate a boundary of a Schmoo plot, comprising selecting a plurality of seed points having a resolution that is less than or equal to ½ the acquisition resolution indicated by a smoothness of a representative Schmoo boundary, performing a coarse boundary search to identify a plurality of test points that are within an acquisition resolution of the boundary, and interpolating the test points that comprise the coarse boundary to produce a fine estimate of the boundary.
    Type: Application
    Filed: December 19, 2005
    Publication date: July 5, 2007
    Inventors: Lokesh Johri, Kaushik Ghosh, Ben Rogel-Favila
  • Publication number: 20070011544
    Abstract: A method including creating a mapping file and a package test program for testing an electronic package. The package comprises a device. The package test program comprises source code for a device test program for testing the device and source code from the mapping file. The device test program source code comprises a reference to a device pin identifier which identifies an associated device pin. Each identified device pin is attached to an associated package pin. Each package pin is identified by a package pin identifier. The mapping file redefines each device pin identifier to be the associated package pin identifier in the package test program. At least one instruction in the package test program created from the device test program source code is configured to attach a tester resource to one of the package pins, and to appropriately activate the tester resource.
    Type: Application
    Filed: June 15, 2005
    Publication date: January 11, 2007
    Inventors: Hsiu-Huan Shen, Jianxiang Chang, Ben Rogel-Favila