Abstract: Technologies for performing dynamic configurations to a transmit scheduler of a network device with minimal downtime are disclosed. The transmit scheduler includes a topology of scheduling nodes. The transmit scheduler identifies, from a number of configuration operations to be executed on one or more of the scheduling nodes, one or more first configuration operations to be executed while the scheduling nodes are active, one or more second configuration operations to be executed while the scheduling nodes are inactive, and one or more third configuration operations to be executed via a cache. The first operations are executed as part of a background process. The second operations are executed while the scheduling nodes are inactive. The third operations are executed via the cache.

Abstract: Examples described herein include configuration of a transmitting network device to identify a source queue-pair identifier in at least some of the packets that are transmitted to an endpoint destination. A network device that receives packets and experiences congestion can determine if a congestion causing packet includes a source queue-pair identifier. If the congestion causing packet includes a source queue-pair identifier, the network device can form and transmit a congestion notification message with a copy of the source queue-pair identifier to the transmitting network device. The transmitting network device can access a context for the congestion causing packet using the source queue-pair identifier without having to perform a lookup to identify the context.

Abstract: Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.

Abstract: Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.

Abstract: Techniques to schedule transmission of a packet from a computing platform include calculating adjustments to portions of the packet to cause corrections to at least one portion of the packet. An adjustment to a scheduled transmission of the packet is made based on the corrections.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: Examples described herein relate to an apparatus including at least one memory and at least one processor communicatively coupled to the at least one memory, the at least one processor to: allocate a scheduler to an egress port and based on unavailability of an egress port, allocate the scheduler to a second egress port to cause any packet allocated to a transmit queue associated with the scheduler to be transmitted using the second egress port. In some examples, a system receives a packet at a port on a network interface, associates a port group with the packet, determines a receive queue for the packet, and copies the packet to the determined receive queue. The port group can be adjusted to remove the port or to add a second port.

Abstract: Systems and methods for multi-architecture computing. Some computing devices may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: Scalable techniques for data transfer between virtual machines (VMs) are described. In an example embodiment, an apparatus may comprise circuitry and memory storing instructions for execution by the circuitry to assign each one of a plurality of public virtual memory spaces to a respective one of a plurality of virtual machines, wherein a first public virtual memory space of the plurality of public virtual memory spaces is assigned to a first virtual machine of the plurality of virtual machines, write, by the first virtual machine to the first public virtual memory space, data to be provided to a second virtual machine of the plurality of virtual machines, and read, by the second virtual machine, the data in the first public virtual memory space.

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: Scalable techniques for data transfer between virtual machines (VMs) are described. the disclosure provides an apparatus including circuitry, a virtual machine management component for execution by the circuitry to define a plurality of public virtual memory spaces and assign each one of the plurality of public virtual memory spaces to a respective one of a plurality of VMs including a first VM and a second VM, and a virtual machine execution component for execution by the circuitry to execute a first virtual machine process corresponding to the first VM and a second virtual machine process corresponding to the second VM, the first virtual machine process to identify data to be provided to the second VM by the first VM and provide the data to the second VM by writing to a public virtual memory space assigned to the first VM. Other embodiments are described and claimed.

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: Examples described herein include configuration of a transmitting network device to identify a source queue-pair identifier in at least some of the packets that are transmitted to an endpoint destination. A network device that receives packets and experiences congestion can determine if a congestion causing packet includes a source queue-pair identifier. If the congestion causing packet includes a source queue-pair identifier, the network device can form and transmit a congestion notification message with a copy of the source queue-pair identifier to the transmitting network device. The transmitting network device can access a context for the congestion causing packet using the source queue-pair identifier without having to perform a lookup to identify the context.

Abstract: Technologies for performing dynamic configurations to a transmit scheduler of a network device with minimal downtime are disclosed. The transmit scheduler includes a topology of scheduling nodes. The transmit scheduler identifies, from a number of configuration operations to be executed on one or more of the scheduling nodes, one or more first configuration operations to be executed while the scheduling nodes are active, one or more second configuration operations to be executed while the scheduling nodes are inactive, and one or more third configuration operations to be executed via a cache. The first operations are executed as part of a background process. The second operations are executed while the scheduling nodes are inactive. The third operations are executed via the cache.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: Examples are disclosed for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may allocate, in a memory of the server, a buffer, a doorbell, and a queue pair accessible to a client remote to the server. For these examples, the network input/output device may assign an Non-Volatile Memory Express (NVMe) namespace context to the client. For these examples, indications of the allocated buffer, doorbell, queue pair, and namespace context may be transmitted to the client. Other examples are described and claimed.

Abstract: Examples are disclosed for command validation for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server. For these examples, elements or modules of the network input/output device may be capable of validating the command and reporting the status of the received command to the client. Other examples are described and claimed.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: Examples are disclosed for forwarding or receiving data segments associated with a large data packets. In some examples, a large data packet may be segmented into a number of data segments having separate headers that include identifiers to associate the data segments with the large data packet. The data segments with separate headers may then be forwarded from a network node via a communication channel. In other examples, the data segments with separate headers may be received at another network node and then recombined to form the large data packet at the other network node. Other examples are described and claimed.

Abstract: Techniques to use descriptors for packet transmit scheduling include grouping a plurality of data descriptors associated with blocks of data with a single descriptor. The single descriptor to include information related to the plurality of data descriptors. The single descriptor to be used to schedule transmission of the blocks of data from a computing platform.