Patents by Inventor Ben-Zion Friedman

Ben-Zion Friedman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9973335
    Abstract: Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device. Data having a destination associated with the first processing element may be received by the input/output device. The exchanged key may be used to encrypt the received data. The encrypted data may then be sent to a buffer maintained at least in part in a memory for the network device. The memory may be arranged to enable sharing of the buffer with at least a second processing element operating on the network device. Examples are also disclosed for the processing element to receive an indication of the storing of the encrypted data in the buffer. The processing element may then obtain the encrypted data from the buffer and decrypt the data using the exchanged key.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 15, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ben-Zion Friedman, Eliezer Tamir, Eliel Louzoun, Ohad Falik
  • Publication number: 20180129770
    Abstract: Technologies for providing FPGA infrastructure-as-a-service include a computing device having an FPGA, scheduler logic, and design loader logic. The scheduler logic selects an FPGA application for execution and the design loader logic loads a design image into the FPGA. The scheduler logic receives a ready signal from the FGPA in response to loading the design and sends a start signal to the FPGA application. The FPGA executes the FPGA application in response to sending the start signal. The scheduler logic may time-share the FPGA among multiple FPGA applications. The computing device may include signaling logic to manage signals between a user process and the FPGA application and DMA logic to manage bulk data transfer between the user process and the FPGA application. The computing device may include a user process linked to an FGPA library executed by a processor of the computing device. Other embodiments are described and claimed.
    Type: Application
    Filed: November 7, 2016
    Publication date: May 10, 2018
    Inventors: Eliezer Tamir, Ben-Zion Friedman, Alexey Puzhevich, Shai Krigman
  • Publication number: 20180091369
    Abstract: Embodiments may be generally directed to techniques to receive rate meter information indicating an occurrence of a rate meter event, the rate meter event determined by a rate meter associated with a network element in a software defined network (SDN) environment. determine a requirement for a service provided by the network element is not met based on the rate meter event detected by the rate meter. Embodiments may also include techniques to determine a corrective action based on the requirement not met, the corrective action to cause the requirement to be met for the service provided by the network element in the SDN environment and cause the correct action to be performed for the network element.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Applicant: INTEL CORPORATION
    Inventors: ANDREW CUNNINGHAM, BEN-ZION FRIEDMAN, JOHN BROWNE, ROBIN GILLER, ALEXANDER LECKEY, ELIEZER TAMIR
  • Publication number: 20180060246
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Application
    Filed: November 3, 2017
    Publication date: March 1, 2018
    Applicant: Intel Corporation
    Inventors: Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B. Crossland, Ohad Falik
  • Patent number: 9866498
    Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Ren Wang, Sameh Gobriel, Christian Maciocco, Tsung-Yuan C. Tai, Ben-Zion Friedman, Hang T. Nguyen, Namakkal N. Venkatesan, Michael A. O'Hanlon, Shrikant M. Shah, Sanjeev Jain
  • Publication number: 20170353385
    Abstract: Examples are disclosed for forwarding or receiving data segments associated with a large data packets. In some examples, a large data packet may be segmented into a number of data segments having separate headers that include identifiers to associate the data segments with the large data packet. The data segments with separate headers may then be forwarded from a network node via a communication channel. In other examples, the data segments with separate headers may be received at another network node and then recombined to form the large data packet at the other network node. Other examples are described and claimed.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 7, 2017
    Applicant: INTEL CORPORATION
    Inventors: Eliezer Tamir, Ben-Zion Friedman
  • Publication number: 20170249281
    Abstract: Examples are disclosed for use of vendor defined messages to execute a command to access a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server for the client to access the storage device. For these examples, elements or components of the network input/output device may be capable of forwarding the command either directly to a Non-Volatile Memory Express (NVMe) controller that controls the storage device or to a manageability module coupled between the network input/out device and the NVMe controller. Vendor specific information may be forwarded with the command and used by either the NVMe controller or the manageability module to facilitate execution of the command. Other examples are described and claimed.
    Type: Application
    Filed: October 10, 2016
    Publication date: August 31, 2017
    Applicant: Intel Corporation
    Inventors: Eliezer Tamir, Ben-Zion Friedman, Steen Larsen
  • Patent number: 9746899
    Abstract: An embodiment may include circuitry that may be capable of performing operations that may include generating, at least in part, at least one message to announce that at least one network node (1) is requesting, at least in part, that one or more transmissions to the at least one network node be postponed, at least in part, and/or (2) is entering, at least in part after issuance of the at least one message, a relatively lower power state relative to a relatively higher power state. Additionally or alternatively, the operations may include, in response, at least in part, to the at least one message, postponing, at least in part, at least one intermediate node at least one transmission (received by the at least one intermediate node) to the at least one network node. Many alternatives, variations, and/or modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Ygdal Naouri, Ben-Zion Friedman, Eliezer Tamir, Eliel Louzoun, Ilango Ganga
  • Patent number: 9742616
    Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Nrupal Jani, Ilango Ganga, Daniel Daly, John Fastabend, Neerav Parikh, Elizabeth Kappler, Brian J. Skerry, Calin Gherghe, Sanjeev Jain, Ben-Zion Friedman
  • Publication number: 20170212762
    Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.
    Type: Application
    Filed: February 6, 2017
    Publication date: July 27, 2017
    Applicant: Intel Corporation
    Inventors: ELIEZER TAMIR, BEN-ZION FRIEDMAN
  • Publication number: 20170187694
    Abstract: Scalable techniques for data transfer between virtual machines (VMs) are described. In an example embodiment, an apparatus may comprise circuitry, a virtual machine management component for execution by the circuitry to define a plurality of public virtual memory spaces and assign each one of the plurality of public virtual memory spaces to a respective one of a plurality of VMs including a first VM and a second VM, and a virtual machine execution component for execution by the circuitry to execute a first virtual machine process corresponding to the first VM and a second virtual machine process corresponding to the second VM, the first virtual machine process to identify data to be provided to the second VM by the first VM and provide the data to the second VM by writing to a public virtual memory space assigned to the first VM. Other embodiments are described and claimed.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: BEN-ZION FRIEDMAN, ELIEZER TAMIR
  • Patent number: 9686190
    Abstract: Examples are disclosed for forwarding or receiving data segments associated with a large data packets. In some examples, a large data packet may be segmented into a number of data segments having separate headers that include identifiers to associate the data segments with the large data packet. The data segments with separate headers may then be forwarded from a network node via a communication channel. In other examples, the data segments with separate headers may be received at another network node and then recombined to form the large data packet at the other network node. Other examples are described and claimed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 20, 2017
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Tamir, Ben-Zion Friedman
  • Publication number: 20170149926
    Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.
    Type: Application
    Filed: February 7, 2017
    Publication date: May 25, 2017
    Inventors: Ren Wang, Sameh Gobriel, Christian Maciocco, Tsung-Yuan C. Tai, Ben-Zion Friedman, Hang T. Nguyen, Namakkal N. Venkatesan, Michael A. O'Hanlon, Shrikant M. Shah, Sanjeev Jain
  • Patent number: 9608842
    Abstract: An embodiment may include circuitry that may provide, at least in part, at least one indication that at least one portion of data is available for processing by at least one data processor. The at least one indication may be provided, at least in part, prior to the entirety of the at least one portion of the data being available for the processing by the at least one data processor. The at least one data processor may begin the processing in response, at least in part, to the at least one indication. Many alternatives, variations, and modifications are possible.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Ygdal Naouri, Ronen Chayat, Ben-Zion Friedman, Parthasarathy Sarangam, Anil Vasudevan, Alain Gravel
  • Patent number: 9577791
    Abstract: Methods and apparatus for implementing notification by network elements of packet drops. In response to determining a packet is to be dropped, a network element such as a switch or router determines the source of the packet and returns a dropped packet notification message to the source. Upon receipt of notification, networking software or embedded hardware on the source causes the dropped packet to be retransmitted. The notification may also be sent from the network element to the destination computer to inform networking software or embedded logic implemented by the destination computer that the packet was dropped and notification to the source has been sent, thus alleviating the destination from needing to send a Selective ACKnowledge (SACK) message to inform the source the packet was not delivered.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: February 21, 2017
    Assignee: Intel Corporation
    Inventors: Eliel Louzoun, Radia Perlman, Ben-Zion Friedman, Ygdal Naouri, Eliezer Tamir
  • Patent number: 9563431
    Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: February 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Tamir, Ben-Zion Friedman
  • Patent number: 9565131
    Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Ren Wang, Sameh Gobriel, Christian Maciocco, Tsung-Yuan C. Tai, Ben-Zion Friedman, Hang T. Nguyen, Namakkal N. Venkatesan, Michael A. O'Hanlon, Shrikant M. Shah, Sanjeev Jain
  • Patent number: 9467512
    Abstract: Examples include client access to a storage medium coupled with a server. A network input/output device for the server receives a remote direct memory access (RDMA) command including a steering tag (S-Tag) from a client remote to the server. For these examples, the network input/output device forwards the RDMA command to a Non-Volatile Memory Express (NVMe) controller and access is provided to a storage medium based on an allocation scheme that assigned the S-Tag to the storage medium. In some other examples, an NVMe controller generates a memory mapping of one or more storage devices controlled by the NVMe controller to addresses for a base address register (BAR) on a Peripheral Component Interconnect Express (PCIe) bus. PCIe memory access commands received by the NVMe controller are translated based on the memory mapping to provide access to the storage device.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: October 11, 2016
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Tamir, Ben-Zion Friedman, Phil C. Cayton, Theodore L. Willke, Frank Berry
  • Patent number: 9467511
    Abstract: Examples are disclosed for use of vendor defined messages to execute a command to access a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server for the client to access the storage device. For these examples, elements or components of the network input/output device may be capable of forwarding the command either directly to a Non-Volatile Memory Express (NVMe) controller that controls the storage device or to a manageability module coupled between the network input/out device and the NVMe controller. Vendor specific information may be forwarded with the command and used by either the NVMe controller or the manageability module to facilitate execution of the command. Other examples are described and claimed.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: October 11, 2016
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Tamir, Ben-Zion Friedman, Steen Larsen
  • Publication number: 20160188344
    Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Applicant: Intel Corporation
    Inventors: ELIEZER TAMIR, BEN-ZION FRIEDMAN