Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.

Abstract: An embodiment includes a device comprising: a substrate; a dielectric layer on the substrate and including a trench; a first portion of the trench including a first material that comprises at least one of a group III-V material and a group IV material; and a second portion of the trench, located between the first portion and the substrate, which includes a second material and an upper region and a lower region; wherein: (a)(i) the second material in the upper region has fewer defects than the second material in the lower region, and (a)(ii) the first material is strained. Other embodiments are described herein.

Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.

Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

Abstract: An interlayer film is deposited on a device layer on a substrate. A contact layer is deposited on the interlayer film. The interlayer film has a broken bandgap alignment to the device layer to reduce a contact resistance of the contact layer to the device layer.

Abstract: A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.

Abstract: A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.

Abstract: Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and mitigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.