Patents by Inventor Benjamin Chu

Benjamin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130062594
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 14, 2013
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yih Jin, Marko Radosavljevic, Willy Rachmady
  • Publication number: 20130032783
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Application
    Filed: October 9, 2012
    Publication date: February 7, 2013
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Mark Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau
  • Patent number: 8368052
    Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 5, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
  • Publication number: 20120326123
    Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: July 10, 2012
    Publication date: December 27, 2012
    Inventors: RAVI PILLARISETTY, Mantu Hudait, Been-Yih Jin, Benjamin Chu-Kung, Robert Chau
  • Publication number: 20120309173
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
    Type: Application
    Filed: July 31, 2012
    Publication date: December 6, 2012
    Inventors: Uday Shah, Benjamin Chu-Kung, Been-Yih Jin, Ravi Pillarisetty, Marko Radosavljevic, Willy Rachmady
  • Patent number: 8283653
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 9, 2012
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau
  • Patent number: 8269209
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Uday Shah, Benjamin Chu-Kung, Been Y. Jin, Ravi Pillarisetty, Marko Radosavljevic, Willy Rachmady
  • Patent number: 8242001
    Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu Hudait, Been-Yih Jin, Benjamin Chu-Kung, Robert Chau
  • Publication number: 20120193609
    Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Inventors: Ravi Pillarisetty, Been-Yin Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
  • Patent number: 8231013
    Abstract: Articles comprising a fibrous support of nanofibers and an interfacially polymerized polymer layer disposed on a surface of the fibrous support are useful, e.g., as fluid separation membranes.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: July 31, 2012
    Assignee: The Research Foundation of State University of New York
    Inventors: Benjamin Chu, Benjamin Hsiao, Kyunghwan Yoon
  • Patent number: 8222166
    Abstract: Membranes suitable for microfiltration, ultrafiltration (UF) and nanofiltration (NF) filters are provided. Such membranes may include a nanofibrous scaffold, optionally in combination with a non-woven substrate and/or a coating of a polymer and a functionalized nanofiller. Suitable membranes may also include a coating of a polymer and a functionalized nanofiller on a substrate, which can include a non-woven membrane, a nanofibrous scaffold, or both.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: July 17, 2012
    Assignee: The Research Foundation of State University of New York
    Inventors: Benjamin Chu, Benjamin S. Hsiao, Dufei Fang, Kwang-Sok Kim
  • Patent number: 8211771
    Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jack Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung
  • Patent number: 8211958
    Abstract: The present disclosure provides polyolefin blends and nanocomposites and methods for their production. In embodiments, a blend or nanocomposite of the present disclosure may include at least one polyolefin and at least one ionic liquid and/or one modified carbon nanofiller. In embodiments, the at least one modified carbon nanotube may be treated with at least one ionic compound.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: July 3, 2012
    Assignee: The Research Foundation of State University of New York
    Inventors: Benjamin Chu, Benjamin S. Hsiao, Hongyang Ma, Nobuyuki Taniguchi
  • Publication number: 20120153263
    Abstract: The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Inventors: Benjamin Chu-Kung, Gilbert Dewey, Marko Radosavljevic, Niloy Mukherjee
  • Publication number: 20120153352
    Abstract: The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the formation of high mobility transistor channels from high indium content alloys, wherein the high indium content transistor channels are achieved with a barrier layer that can substantially lattice match with the high indium content transistor channel.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 21, 2012
    Inventors: Gilbert Dewey, Niloy Mukherjee, Marko Radosavljevic, Benjamin Chu-Kung
  • Publication number: 20120145740
    Abstract: Currently, pharmaceutical tablets are distributed in bottles that must be opened and closed; the pill-dispenser presented here aims to simplify the process for taking pills by releasing a tablet at the click of a button. Additional features of the dispenser are child-resistant capabilities, which may be considered a distinct claim, and use of click-pen mechanisms; furthermore, it can be used as a conventional open/close medication bottle, but doing so will disable its dispensing function. The purpose of this document is to lawfully protect future work on the design, development, and production of this device.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Inventor: Benjamin Chu
  • Patent number: 8193523
    Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Been-Yih Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
  • Patent number: 8168508
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yih Jin, Marko Radosavljevic, Willy Rachmady
  • Patent number: 8115235
    Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: February 14, 2012
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Titash Rakshit, Mantu Hudait, Marko Radosavljevic, Gilbert Dewey, Benjamin Chu-Kung
  • Publication number: 20120032146
    Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: October 17, 2011
    Publication date: February 9, 2012
    Inventors: Ravi Pillarisetty, Mantu Hudait, Been-Yin Jin, Benjamin Chu-Kung, Robert Chau