Patents by Inventor Benjamin D. Briggs

Benjamin D. Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140606
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Application
    Filed: December 26, 2024
    Publication date: May 1, 2025
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Publication number: 20250140611
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Application
    Filed: November 13, 2024
    Publication date: May 1, 2025
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee, Theodorus E. Standaert
  • Publication number: 20250117561
    Abstract: A semiconductor device may include a substrate. The semiconductor device may also include a dielectric material characterized, at least in part, by a dielectric constant. The semiconductor device may include a metallic pathway formed in the dielectric material. The semiconductor device may include a region about the metallic pathway of the semiconductor device may include a plurality of air gaps within the dielectric material and arranged three-dimensionally throughout the region, where the region may include a lower dielectric constant than the dielectric constant of the dielectric material.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Applicant: Applied Materials, Inc.
    Inventor: Benjamin D. Briggs
  • Publication number: 20250046652
    Abstract: A method includes obtaining a base structure including a stack of dielectric layers disposed on a substrate. The stack of dielectric layers includes a first photosensitive dielectric layer including a first photosensitive dielectric material sensitive to a first radiation dose, a second photosensitive dielectric layer including a second photosensitive dielectric material sensitive to a second radiation dose different from the first radiation dose, and a barrier layer disposed between the first photosensitive dielectric layer and the second photosensitive dielectric layer. The method further includes forming a dual damascene structure from the base structure using a dual damascene process.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Inventors: Benjamin D. Briggs, William Charles, Gillian Micale
  • Patent number: 12218003
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: February 4, 2025
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Publication number: 20250029835
    Abstract: Exemplary semiconductor processing methods may include performing a treatment operation on a substrate housed within a first processing region of a first semiconductor processing chamber. The methods may include providing a nitrogen-containing precursor to the first processing region. The methods may include forming plasma effluents of the nitrogen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the nitrogen-containing precursor. The contacting may nitride a surface of the substrate. The methods may include transferring the substrate from the first processing region of the first semiconductor processing chamber to a second processing region of a second semiconductor processing chamber. The methods may include providing one or more deposition precursors to the second processing region. The methods may include contacting the substrate with the one or more deposition precursors. The contacting may deposit a layer of dielectric material on the substrate.
    Type: Application
    Filed: July 12, 2024
    Publication date: January 23, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Ryan Ley, Archana Kumar, Michel El Khoury Maroun, Benjamin D. Briggs
  • Patent number: 12183634
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: December 31, 2024
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee, Thedorus E. Standaert
  • Publication number: 20240395702
    Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.
    Type: Application
    Filed: August 2, 2024
    Publication date: November 28, 2024
    Inventors: Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla
  • Publication number: 20240347383
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Application
    Filed: October 19, 2023
    Publication date: October 17, 2024
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee, Thedonus E. Standaert
  • Patent number: 12087685
    Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: September 10, 2024
    Assignee: Tessera LLC
    Inventors: Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla
  • Patent number: 12055821
    Abstract: Processing methods may be performed to form a pixel isolation structure on a semiconductor substrate. The method may include forming a pixel isolation bilayer on the semiconductor substrate. The pixel isolation bilayer may include a high-k layer overlying a stopping layer. The method may include forming a lithographic mask on a first region of the pixel isolation bilayer. The method may also include etching the pixel isolation bilayer external to the first region. The etching may reveal the semiconductor substrate. The etching may form the pixel isolation structure.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: August 6, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Lan Yu, Benjamin D. Briggs, Tyler Sherwood, Zihao Yang
  • Publication number: 20240096693
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Application
    Filed: April 25, 2023
    Publication date: March 21, 2024
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 11908678
    Abstract: Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Lan Yu, Benjamin D. Briggs, Tyler Sherwood, Raghav Sreenivasan, Joseph Salfelder
  • Patent number: 11880052
    Abstract: Processing methods may be performed to form a grounded mirror structure on a semiconductor substrate. The methods may include revealing a metal layer. The metal layer may underlie a spacer layer. The metal layer may be revealed by a dry etch process. The method may include forming a mirror layer overlying the spacer layer and the metal layer. The mirror layer may contact the metal layer. The method may also include forming an oxide inclusion overlying a portion of the mirror layer. The portion of the mirror layer may be external to the spacer layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Lan Yu, Benjamin D. Briggs, Tyler Sherwood, Raghav Sreenivasan
  • Patent number: 11881539
    Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Lan Yu, Benjamin D. Briggs, Tyler Sherwood, Raghav Sreenivasan
  • Publication number: 20240014133
    Abstract: An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 11, 2024
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Patent number: 11869783
    Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James Stathis
  • Publication number: 20230409692
    Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Spyridon Skordas
  • Patent number: 11837501
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: December 5, 2023
    Assignee: TESSERA LLC
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee, Theodorus E. Standaert
  • Publication number: 20230335438
    Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.
    Type: Application
    Filed: November 22, 2022
    Publication date: October 19, 2023
    Inventors: Benjamin D. Briggs, Elbert Huang, Takeshi Nogami, Christopher J. Penny