Patents by Inventor Benjamin D. Briggs

Benjamin D. Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11158584
    Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs
  • Patent number: 11138890
    Abstract: The present invention may receive a plurality of unlock instructions based on determining a location is secured from access by the drone. The present invention may use the plurality of received unlock instructions to access the location with an access device while determining the drone is present at the drop off location. The present invention may use the plurality of received unlock instructions to re-secure the location with the access device when determining successful delivery of a package by the drone, and may monitor a security of the location.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Sipolins
  • Patent number: 11132712
    Abstract: Three-dimensional positional spatial olfaction for virtual marketing associates a product with a product location within a virtual reality environment and identifies a product aroma associated with the product. A distance and a direction from the product location to a positional presence of a participant within the virtual reality environment is determined, and the product aroma is delivered to the participant in accordance with the distance and the direction. Delivery of the product aroma to the participant in accordance with the distance and the direction is used to lead the participant through the virtual reality environment to the product location where an interface for obtaining a physical copy of the product is displayed to the participant.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christoper J. Penny, Michael Rizzolo, Aldis Sipolins
  • Patent number: 11101172
    Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Benjamin D. Briggs, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Publication number: 20210249288
    Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James Stathis
  • Patent number: 11081388
    Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kisik Choi, Koichi Motoyama, Ashim Dutta, Iqbal R. Saraf, Benjamin D. Briggs
  • Publication number: 20210217653
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 11049744
    Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James Stathis
  • Patent number: 11018090
    Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Rizzolo, Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs
  • Patent number: 11004790
    Abstract: A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10991619
    Abstract: A method for fabricating a semiconductor device to account for misalignment includes forming a top via on a first conductive line formed on a substrate, forming liners each using a first dielectric material, including forming first and second liners to a first height along sidewalls of the top via, forming dielectric layers, including forming first and second dielectric layers on the first conductive line to the first height and adjacent to the first and second liners, respectively, recessing the top via to a second height, and forming an additional dielectric layer on the recessed top via to the first height using a second dielectric material. The first and second dielectric materials are selected to compensate for potential misalignment between the first conductive line and the top via.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Lawrence A. Clevenger, Benjamin D. Briggs, Brent A. Anderson, Chih-Chao Yang
  • Patent number: 10978393
    Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Takeshi Nogami, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10978342
    Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Huai Huang, Takeshi Nogami, Alfred Grill, Benjamin D. Briggs, Nicholas A. Lanzillo, Christian Lavoie, Devika Sil, Prasad Bhosale, James Kelly
  • Patent number: 10971030
    Abstract: A system and method perform remote physical training. The method includes receiving movements performed by an operator who is remotely located, and presenting the movements of the operator as movements performed by an avatar representing the operator in a virtual reality environment. The method also includes remotely monitoring the movements of the avatar, and providing real-time feedback on the movements to the operator.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis G. Sipolins
  • Patent number: 10957582
    Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Terry A. Spooner, Theodorus E. Standaert
  • Patent number: 10957646
    Abstract: A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui, Ruqiang Bao, Gangadhara Raja Muthinti, Lawrence A. Clevenger
  • Patent number: 10957581
    Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Terry A. Spooner, Theodorus E. Standaert
  • Publication number: 20210082758
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Application
    Filed: November 9, 2020
    Publication date: March 18, 2021
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
  • Publication number: 20210083179
    Abstract: Encapsulation topography-assisted techniques for forming self-aligned top contacts in MRAM devices are provided. In one aspect, a method for forming an MRAM device includes: forming MTJs on interconnects embedded in a first dielectric; depositing an encapsulation layer over the MTJs; burying the MTJs in a second dielectric; patterning a trench in the second dielectric over the MTJs exposing the encapsulation layer over tops of the MTJs which creates a topography at the trench bottom; forming a metal line in the trench over the topography; recessing the metal line which breaks up the metal line into segments separated by exposed peaks of the encapsulation layer; recessing the exposed peaks of the encapsulation layer to form recesses at the tops of the MTJs; and forming self-aligned contacts in the recesses. An MRAM device is also provided.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Michael Rizzolo, Nicholas Anthony Lanzillo, Benjamin D. Briggs, Lawrence A. Clevenger
  • Patent number: 10943866
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha