Patents by Inventor Benjamin D. Briggs

Benjamin D. Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672707
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: June 2, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath, Chih-Chao Yang
  • Publication number: 20200161175
    Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include a top via integration scheme. The top via integration scheme integrally forms the via on top of trench. Thus, the via is fully aligned and can be of a desired critical dimension.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs, Brent Anderson
  • Publication number: 20200161239
    Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10658585
    Abstract: Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Lawrence A. Clevenger, Chih-Chao Yang, Benjamin D. Briggs
  • Patent number: 10658233
    Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Benjamin D. Briggs, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10651078
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 12, 2020
    Assignee: Tessera, Inc.
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Publication number: 20200136028
    Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 30, 2020
    Inventors: Nicholas A. Lanzillo, Benjamin D. Briggs, Chih-Chao Yang, Hsueh-Chung Chen, Lawrence A. Clevenger
  • Publication number: 20200135560
    Abstract: A method for manufacturing a semiconductor device includes forming a conductive via extending vertically from a conductive layer, and depositing a first dielectric layer on the conductive layer and on lateral sides the conductive via. In the method, the conductive via is recessed with respect to a top surface of the first dielectric layer. An etch stop layer is deposited on the top surface of the first dielectric layer and on a top surface of the conductive via, and a second dielectric layer is deposited on the etch stop layer. The method also includes removing portions of the etch stop layer and the second dielectric layer to create a plurality of trenches spaced apart from each other. A trench of the plurality of trenches is formed over and exposes at least part of the conductive via, and a conductive material is deposited in the plurality of trenches.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Benjamin D. Briggs
  • Patent number: 10636706
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 28, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
  • Publication number: 20200125969
    Abstract: The present invention provides for a cognitive system using an autonomous vehicle includes a plurality of sensors configured to obtain the weather forecast for a pollution detectable area; a cognitive input to determine the pollution detectable area having highest sensitivity of pollution; a light detecting and ranging system configured to spatially probe pollution levels distributed in the pollution detectable area; an evaluation system to evaluate the probed pollution levels in the pollution detectable area; and a recommendation system for recommending an action to be taken based on evaluation system results of the probed pollution levels in the pollution detectable area, wherein the pollution levels are detected based light emitted by the light detecting and ranging system.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 23, 2020
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo
  • Publication number: 20200126854
    Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: Koichi Motoyama, Benjamin D. Briggs, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10629009
    Abstract: An unmanned vehicle is identified. One or more specifications of the unmanned vehicle are retrieved in response to the identification. A first characteristic of the unmanned vehicle is observed. The observed first characteristic is compared to the retrieved specifications. A compliance standard of the unmanned vehicle is determined. The determination is based on the comparison.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yuk L. Chan, Eileen P. Tedesco, Kyle Gilbertson, Daniel F. Hogerty, Lawrence A. Clevenger, Benjamin D. Briggs
  • Patent number: 10629478
    Abstract: A method of forming a semiconductor device includes forming a dielectric spacer along sidewalls of a plurality of interconnect openings extending through a sacrificial dielectric layer and a first dielectric layer until a top portion of a first conductive material, the dielectric spacer includes a dielectric material having a dielectric constant higher than a dielectric constant of the sacrificial dielectric layer and higher than a dielectric constant of the first dielectric layer, conformally depositing a barrier liner within the plurality of interconnect openings above and in direct contact with the dielectric spacer, filling the interconnect openings with a second conductive material, removing the sacrificial dielectric layer to expose portions of the dielectric spacer above the first dielectric layer, and reducing a thickness of exposed portions of the dielectric spacer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Huai Huang, Christopher J. Penny, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 10615119
    Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10606231
    Abstract: A computer-mediated physical damping feedback system includes a motion damping device, a voltage conversion controller, and a voltage generator controller. The motion damping device is worn by a participant present in a real-world environment, and is configured to vary a moveable flexibility of the participant in response to receiving an electrical voltage. The voltage conversion controller is in signal communication with a computer-mediated environment engine (CMEE) controller, and is configured to determine a voltage level of the electrical voltage based at least in part on the interaction between the participant and a computer-mediated environment. The voltage generator controller is in signal communication with the motion damping device and the voltage conversion controller. The voltage generator controller is configured to generate the electrical voltage at the voltage level that induces the stress applied by the motion damping device.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Sipolins
  • Publication number: 20200098499
    Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Nicholas A. Lanzillo, Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert, Lawrence A. Clevenger, James Stathis
  • Publication number: 20200091079
    Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Takeshi Nogami, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10593506
    Abstract: A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo
  • Publication number: 20200081761
    Abstract: Methods and systems for printing accurate three-dimensional structures include printing an original three-dimensional structure according to an original three-dimensional model. The original three-dimensional model is adjusted to reduce measured differences between the printed three-dimensional structure and the original three-dimensional model, by adding material to the original three-dimensional model in proportion to an amount of thermal contraction in a region. An adjusted three-dimensional structure is printed according to the adjusted three-dimensional model.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis G. Sipolins
  • Patent number: 10586767
    Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui, Ruqiang Bao, Gangadhara Raja Muthinti, Lawrence A. Clevenger