Abstract: An aspect of the disclosure includes a security system and method having a key with nanoscale features. The key includes a body. At least one pattern member disposed on the body, the pattern member formed using a directed self-assembly polymer to define a pattern of random feature structures thereon, the feature structures having a width of less than 100 nanometers.

Abstract: An aspect of the disclosure includes a security system and method having a key with nanoscale features. The key includes a body. At least one pattern member disposed on the body, the pattern member formed using a directed self-assembly polymer to define a pattern of random feature structures thereon, the feature structures having a width of less than 100 nanometers.

Abstract: Techniques for motivating a user during a workout using different coaching styles are provided. In one aspect, a method for motivational coaching of a user during workout sessions includes the steps of: selecting a coaching style for the user based on input from the user and from coaching styles used for at least one other user; determining, during a workout session, whether the coaching style should be changed to enhance performance of the user based on data obtained from the user via a mobile device worn by the user; changing the coaching style if it is determined that the coaching style should be changed to enhance performance of the user; continuing with a current coaching style if it is determined that the coaching style should not be changed; and providing feedback to the user during the workout session based on the coaching style.

Abstract: Techniques are provided for alerting drivers of hazardous driving conditions using the sensing capabilities of wearable mobile technology. In one aspect, a method for alerting drivers of hazardous driving conditions includes the steps of: collecting real-time data from a driver of a vehicle, wherein the data is collected via a mobile device worn by the driver; determining whether the real-time data indicates that a hazardous driving condition exists; providing feedback to the driver if the real-time data indicates that a hazardous driving condition exists, and continuing to collect data from the driver in real-time if the real-time data indicates that a hazardous driving condition does not exist. The real-time data may also be collected and used to learn characteristics of the driver. These characteristics can be compared with the data being collected to help determine, in real-time, whether the driving behavior is normal and whether a hazardous driving condition exists.

Abstract: A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer, conformally depositing a barrier layer on the dielectric layer and on sides and a bottom of each one of the plurality of openings, depositing a contact layer on the barrier layer in each one of the plurality of openings, removing a portion of each contact layer from each one of the plurality of openings, and removing a portion of the barrier layer from each one of the plurality of openings, wherein at least the removal of the portion of the barrier layer is performed using an etchant including: (a) a compound selected from group consisting of -azole, -triazole, and combinations thereof; (b) a compound containing one or more peroxy groups; (c) one or more alkaline metal hydroxides; and (d) water.

Abstract: A method for forming chamferless vias comprises receiving a substrate stack comprising a hard mask layer, a porous dielectric layer underlying the hard mask layer, a cap layer underlying the dielectric layer, and a conductive layer underlying the cap layer. The hard mask layer is opened to reveal a portion of the dielectric layer. A plurality of vias are opened to extend through the dielectric layer and the cap layer. A pore filling material comprising a thermally decomposable polymer is deposited into the vias. The pore filling material in the vias is hardened and driven into the pores of the dielectric layer adjacent to the vias by an annealing process. The hard mask layer is removed. A trench is patterned and etched coincident with the vias. A dissipation process is conducted to remove the pore filling material.

Abstract: Techniques for leveraging the capabilities of wearable mobile technology to collect data and to provide real-time feedback to an orator about his/her performance and/or audience interaction are provided. In one aspect, a method for providing real-time feedback to a speaker making a presentation to an audience includes the steps of: collecting real-time data from the speaker during the presentation, wherein the data is collected via a mobile device worn by the speaker; analyzing the real-time data collected from the speaker to determine whether corrective action is needed to improve performance; and generating a real-time alert to the speaker suggesting the corrective action if the real-time data indicates that corrective action is needed to improve performance, otherwise continuing to collect data from the speaker in real-time. Real-time data may also be collected from members of the audience and/or from other speakers (if present) via wearable mobile devices.

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

Abstract: The present invention provides techniques for leveraging the sensing capabilities of wearable mobile technology, such as a smartwatch, to provide real-time harm prevention. In one aspect of the invention, a method for harm prevention is provided. The method includes the steps of: collecting real-time data from at least one user, wherein the data is collected via a mobile device worn by the user (e.g., a smartwatch); analyzing the real-time data collected from the user to determine whether the real-time data indicates an emergency situation exists; and undertaking an appropriate action if the real-time data indicates that an emergency situation exists, otherwise continuing to collect data from the user in real-time. Third party data relating to potential source of harm to the user may also be obtained (e.g., from a weather service, newsfeeds, etc.

Abstract: Techniques for modifying user behavior and screening for impairment using a mobile feedback controller, such as a smartwatch, are provided. In one aspect, a method for monitoring a user includes the steps of: collecting real-time data from the user, wherein the data is collected via a mobile feedback controller worn by the user; determining whether the data collected from the user indicates impairment; determining appropriate corrective actions to be taken if the data collected from the user indicates impairment, otherwise continuing to collect data from the user in real-time; determining whether any action is needed; and undertaking the appropriate corrective actions if action is needed, otherwise continuing to collect data from the user in real-time.

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.

Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.

Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.

Abstract: A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first airgaps. A protection layer is formed in divots in the pinch off layer. The protection layer and the pinch off layer are planarized to form a surface where the protection layer remains in the divots. An interlevel dielectric layer (ILD) is deposited on the surface. The ILD and the pinch off layer are etched using the protection layer as an etch stop to align a via and expose the interconnect structure through the via.

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.