Abstract: A computer-implemented method includes tracking, using a computer processor, a position of a receiver in real space. A set of images is generated, using the computer processor, where the set of images represents a position of the receiver in virtual space, and where the position of the receiver in virtual space corresponds to the position of the receiver in real space. The set of images is transmitted, using a light fidelity (LiFi) communication system, to a display.

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Abstract: Aspects of the disclosure include method of making semiconductor structures. Aspects include providing a semiconductor structure including a plurality of spacer, an organic planarization layer, and a SiARC layer. Aspects also include forming an inverted mask on the semiconductor structure, the inverted mask including an inverted mask opening above a portion of the plurality of spacers and a portion of the TiN layer. Aspects also include eroding the portion of the plurality of spacers below the inverted mask opening. Aspects also include depositing a fill material masking the portion of the plurality of spacers below the inverted mask opening and the portion of the TiN layer below the inverted mask opening to generate a masked TiN layer segment and an unmasked TiN layer segment and removing a portion of the unmasked TiN layer segment.

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.

Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma- attack immune material.

Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.

Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.

Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.

Abstract: Techniques are provided for alerting drivers of hazardous driving conditions using the sensing capabilities of wearable mobile technology. In one aspect, a method for alerting drivers of hazardous driving conditions includes the steps of: collecting real-time data from a driver of a vehicle, wherein the data is collected via a mobile device worn by the driver; determining whether the real-time data indicates that a hazardous driving condition exists; providing feedback to the driver if the real-time data indicates that a hazardous driving condition exists, and continuing to collect data from the driver in real-time if the real-time data indicates that a hazardous driving condition does not exist. The real-time data may also be collected and used to learn characteristics of the driver. These characteristics can be compared with the data being collected to help determine, in real-time, whether the driving behavior is normal and whether a hazardous driving condition exists.

Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.

Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: An aspect of the disclosure includes a security system and method having a key with nanoscale features. The key includes a body. At least one pattern member disposed on the body, the pattern member formed using a directed self-assembly polymer to define a pattern of random feature structures thereon, the feature structures having a width of less than 100 nanometers.

Abstract: A method for forming interconnect structures includes forming a barrier material over a dielectric layer having a trench, the barrier layer being disposed on sidewalls and horizontal surfaces of the trench, depositing an interconnect layer over the barrier layer to form an interconnect structure, recessing the interconnect layer down to a surface of the barrier layer using a chemical mechanical planarization process, and planarizing the barrier layer and the interconnect layer using a wet etch process to form a coplanar surface to prevent dishing or divots in the interconnect structure.

Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.