Abstract: Provided is an authentication method, the method comprising sending, by an entity, to a chip, at least one request for getting data; receiving, by the entity, from the chip, data; and, authenticating, by the entity, based on the received data, a family relating to the chip. Other embodiments disclosed.

Abstract: Provided is a contactless electronic system configured for contactless communications with a reader over an electromagnetic field and comprising a power supply, a current monitor, a processing system comprising a hardware processor configured for performing operations, a dynamic extra current loader and a clock generator, wherein the power supply includes a clamp circuit, and wherein, continuously until the end of an execution phase of said hardware processor. The current monitor is configured for determining the maximal current Imax that can be provided by the power supply to the processing system from the electromagnetic field by comparing a current into the clamp circuit to at least one predetermined threshold. Other embodiments disclosed.

Abstract: Provided is a an electronic system (1) comprising a plurality of sub blocks (21, 22, . . . ), a differential amplifier (3), a voltage regulation loop comprising a first transistor (40) and a variable resistor (5), and a plurality of additional transistors (41, 42, . . . ). The input reference voltage (VRF) and the variable resistor are configured such that a first sub block (21) is supplied with its required power supply output voltage (VDD1) by the transistor to which it is connected. The amplifier is configured to output on each of its outputs a power supply reference voltage (VG1, VG2 . . . ) such that each sub block (22, . . . ) other than the first sub block is supplied with its required power supply output voltage (VDD2 . . . ) by the transistor to which it is connected.

Abstract: Provided is a method for generating a physical unclonable function PUF response by a PUF circuit of an electronic device, said PUF circuit comprising pairs of electronic components called PUF primitives implementing said physical unclonable function, by obtaining a challenge (S1), generating PUF output bits (S2) by applying said physical unclonable function to said obtained challenge, and generating said PUF response (S3) from said generated PUF output bits verifying ? > ?? +|T| or ? < -?? -|T| with ?? a predetermined threshold. In some embodiments it maximizes a PUF response entropy based only on the analog differential values generated by the comparators of the electronic device. Other embodiments disclosed.

Abstract: Provided is an electronic device and a method thereof for repairing response bits of a physical unclonable function of an electronic device, said physical unclonable function outputting said response bits and additional output bits. The method includes generating a PUF response from said response bits (S1), detecting an error in the PUF response (S2), determining erroneous response bits of the PUF response (S3), determining a match (S4) between each determined erroneous response bit and a selected additional output bit such that replacing the erroneous response bits by the matching additional output bits corrects the error in the PUF response, storing said determined match in a repair list (S5), and replacing (S6) in the PUF response said erroneous response bits with the matching additional output bits in the repair list. Other embodiments disclosed.

Abstract: A method of identifying primitives for implementing a physical unclonable function providing a response representative of a device comprising a plurality of primitives coupled in pairs, said primitives being configured for being one-time programmable through application of a burning energy to said primitives, by selecting a subset of the pairs, assessing a difference between electrical characteristics values provided by primitives belonging to each pair of said subset, qualifying all pairs of primitives for which the assessed difference is higher than a reference threshold, and identifying said qualified pairs of primitives comprising programming at least one primitive of each pair of primitives for which the assessed difference is lower than said reference threshold, by applying a burning energy to said at least one primitive so as to differentiate qualified pairs of primitives from those that are not qualified.

Abstract: Provided is a an electronic system (1) comprising a plurality of sub blocks (21, 22, . . . ), a differential amplifier (3), a voltage regulation loop comprising a first transistor (40) and a variable resistor (5), and a plurality of additional transistors (41, 42, . . . ). The input reference voltage (VRF) and the variable resistor are configured such that a first sub block (21) is supplied with its required power supply output voltage (VDD1) by the transistor to which it is connected. The amplifier is configured to output on each of its outputs a power supply reference voltage (VG1, VG2 . . . ) such that each sub block (22, . . . ) other than the first sub block is supplied with its required power supply output voltage (VDD2 . . . ) by the transistor to which it is connected.

Abstract: Provided is a contactless electronic system configured for contactless communications with a reader over an electromagnetic field and comprising a power supply, a current monitor, a processing system comprising a hardware processor configured for performing operations, a dynamic extra current loader and a clock generator. The current monitor is configured for determining maximal current Imax that can be provided by the power supply to the processing system from the electromagnetic field, and is configured for comparing, during an execution phase of said hardware processor, said determined maximal current Imax and a current drawn by the processing system.

Abstract: A method, cryptographic device, and computer readable memory with instructions, for generating a cryptographic key from at least one prime number, by performing during runtime of the cryptographic device by obtaining from memory a challenge and at least one associated increment number, generating a seed by applying a Physically Unclonable function to said obtained challenge, generating at least one prime number from said generated seed by performing said cryptographic prime numbers generation algorithm and by performing therein as many incrementation steps as said obtained at least one increment number, and generating the cryptographic key from the generated prime number.

Abstract: A method of identifying primitives for implementing a physical unclonable function providing a response representative of a device comprising a plurality of primitives coupled in pairs, said primitives being configured for being one-time programmable through application of a burning energy to said primitives, by selecting a subset of the pairs, assessing a difference between electrical characteristics values provided by primitives belonging to each pair of said subset, qualifying all pairs of primitives for which the assessed difference is higher than a reference threshold, and identifying said qualified pairs of primitives comprising programming at least one primitive of each pair of primitives for which the assessed difference is lower than said reference threshold, by applying a burning energy to said at least one primitive so as to differentiate qualified pairs of primitives from those that are not qualified.

Abstract: A method, cryptographic device, and computer readable memory with instructions, for generating a cryptographic key from at least one prime number, by performing during runtime of the cryptographic device by obtaining from memory a challenge and at least one associated increment number, generating a seed by applying a Physically Unclonable function to said obtained challenge, generating at least one prime number from said generated seed by performing said cryptographic prime numbers generation algorithm and by performing therein as many incrementation steps as said obtained at least one increment number, and generating the cryptographic key from the generated prime number.

Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

Abstract: A method and a system for qualifying an integrated circuit according to a parasitic supply peak detector that it contains, including: supply of the integrated circuit to be tested under at least a first voltage; checking of a starting of the circuit; application of at least one first noise peak on the circuit power supply, while respecting an amplitude and time gauge; and comparison of average currents consumed by the circuit before and after the peak.

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: A circuit for detecting noise peaks on the power supply of an electronic circuit, including at least a first transistor having its control terminal connected to a terminal of application of a first potential of a supply voltage of the circuit and having a first conduction terminal connected to a terminal of application of a second potential via at least one first resistive element, the second conduction terminal of the first transistor providing the result of the detection.

Abstract: A device includes a serial port for connecting as a slave to a master device through a serial link. The device further includes a detection circuit for detecting the presence of an impedance of the master device, linked to a terminal of the serial port. The device can be used with microprocessor cards comprising a USB port.

Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.