Patents by Inventor Benjamin H. Ashmore
Benjamin H. Ashmore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160308552Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: ApplicationFiled: April 19, 2016Publication date: October 20, 2016Inventor: Benjamin H. Ashmore, JR.
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Patent number: 9344109Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: GrantFiled: March 9, 2015Date of Patent: May 17, 2016Inventor: Benjamin H. Ashmore, Jr.
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Publication number: 20150244392Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: ApplicationFiled: March 9, 2015Publication date: August 27, 2015Inventor: Benjamin H. Ashmore, JR.
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Patent number: 9013338Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: GrantFiled: June 21, 2012Date of Patent: April 21, 2015Inventor: Benjamin H. Ashmore, Jr.
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Publication number: 20120256775Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: ApplicationFiled: June 21, 2012Publication date: October 11, 2012Inventor: Benjamin H. Ashmore, JR.
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Patent number: 8228220Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: GrantFiled: May 3, 2011Date of Patent: July 24, 2012Inventor: Benjamin H. Ashmore, Jr.
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Publication number: 20110205094Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Inventor: Benjamin H. Ashmore, JR.
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Patent number: 7956777Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: GrantFiled: June 1, 2009Date of Patent: June 7, 2011Inventor: Benjamin H. Ashmore, Jr.
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Publication number: 20090237280Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: ApplicationFiled: June 1, 2009Publication date: September 24, 2009Inventor: Benjamin H. Ashmore, JR.
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Patent number: 7551109Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.Type: GrantFiled: March 13, 2008Date of Patent: June 23, 2009Inventor: Benjamin H Ashmore, Jr.
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Patent number: 7069485Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple TAP read or write operations operations.Type: GrantFiled: October 28, 2003Date of Patent: June 27, 2006Assignee: Texas Instruments IncorporatedInventors: Lee Doyle Whetsel, Jr., Benjamin H. Ashmore, Jr.
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Publication number: 20040093534Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.Type: ApplicationFiled: October 28, 2003Publication date: May 13, 2004Inventors: Lee Doyle Whetsel, Benjamin H. Ashmore
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Patent number: 6675333Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.Type: GrantFiled: November 21, 2000Date of Patent: January 6, 2004Assignee: Texas Instruments IncorporatedInventors: Lee Doyle Whetsel, Jr., Benjamin H. Ashmore, Jr.
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Patent number: 6158035Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.Type: GrantFiled: May 26, 1999Date of Patent: December 5, 2000Assignee: Texas Instruments IncorporatedInventors: Lee Doyle Whetsel, Jr., Benjamin H. Ashmore, Jr.
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Patent number: 6085344Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.Type: GrantFiled: September 23, 1997Date of Patent: July 4, 2000Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Jr., Benjamin H. Ashmore, Jr.
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Patent number: 5687179Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.Type: GrantFiled: March 29, 1995Date of Patent: November 11, 1997Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Jr., Benjamin H. Ashmore, Jr.
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Patent number: 5491660Abstract: The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder (MID), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and an optional subroutine stack (SS) to allow function calls. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip. Control instructions are easily modified to compensate for process and structure enhancements are made during the production lifetime of an integrated-circuit memory.Type: GrantFiled: November 18, 1994Date of Patent: February 13, 1996Assignee: Texas Instruments IncorporatedInventor: Benjamin H. Ashmore, Jr.
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Patent number: 5313432Abstract: A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.Type: GrantFiled: November 12, 1991Date of Patent: May 17, 1994Assignee: Texas Instruments IncorporatedInventors: Sung-Wei Lin, John F. Schreck, Phat C. Truong, David J. McElroy, Harvey J. Stiegler, Benjamin H. Ashmore, Jr., Manzur Gill
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Patent number: 5287536Abstract: A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded.Type: GrantFiled: January 22, 1993Date of Patent: February 15, 1994Assignee: Texas Instruments IncorporatedInventors: John F. Schreck, Phat C. Truong, Benjamin H. Ashmore, Jr., Harvey J. Steigler
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Patent number: 5267204Abstract: A method and circuitry for masking data in a memory device are provided, which detect whether at least one failed bit location within the memory device is equal to a corresponding bit within input data. Data is written to the memory device as selectively inverted from the input data based upon whether the failed bit location is equal to the corresponding bit. An inversion bit within the memory device is selectively set to indicate whether the written data is inverted from the input data.Type: GrantFiled: October 18, 1991Date of Patent: November 30, 1993Assignee: Texas Instruments IncorporatedInventor: Benjamin H. Ashmore, Jr.