Abstract: A line unit, used in a line shelf having a line shelf processor and common logic, is provided with an EEPROM device for storing information relative to the line unit. The stored information includes line unit type identification codes, auto provisioning data, gain and equalization adjustment data and signaling translation tables. The data contained within the EEPROM may be utilized by the line shelf processor to provide automatic initialization and provisioning of the line unit when first inserted into the line shelf, and automatic signaling translation so that line unit signaling becomes compatible with a transmission facility connected to the line shelf. The need for factory preset resistors installed in the line unit may be eliminated by storing within the EEPROM a required gain setting.

Abstract: A series inverter, high voltage capacitor charging circuit includes a current sensor for sensing the current through the load circuit. The sensed current is used to vary the gating frequency of SCRs and to preclude firing of an SCR pair until another SCR pair is in a stable off condition. The gating of each SCR pair is delayed by an amount of time determined by a control capacitor charging circuit. That charging circuit is inhibited as long as one of the SCRs is conducting and once the load voltage has reached a predetermined level. The time constant of that charging circuit is longer if insufficient reverse bias is applied to an SCR for quick turn-off of the SCR. The current sensing thresholds of common base transistors depend on whether forward or reflective current is being sensed. A series capacitor in the load circuit is discharged prior to a first cycle of current flow from the dc supply.